Datasheet
LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 102 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
12.2 16-bit ADC characteristics
[1] Based on characterization; not tested in production.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[3] <TBD> The input resistance of ADC channels <tbd> to <tbd> is higher than ADC channels <tbd> to <tbd>.
[4] C
ia
represents the external capacitance on the analog input channel for sampling speeds of <tbd>
Msamples/s.
[5] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width.
See Figure 28.
[6] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 28.
[7] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 28.
[8] The full-scale error voltage or gain error (E
G
) is the difference between the straight-line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 28.
[9] T
amb
= 25 C; maximum sampling frequency f
s
= <tbd> Msamples/s and analog input capacitance
C
ia
= <tbd> pF.
[10] Input impedance Z
i
is inversely proportional to the sampling frequency and the total input capacity including
C
ia
and C
io
: Z
i
1 / (f
s
C
i
). See Table 21 for C
io
. See Figure 29.
Table 41. 16-bit ADC static characteristics
T
amb
= 40 C to +105 C; V
DD
= 1.8 V to 3.6 V; VREFP = V
DDA
; V
SSA
= 0; VREFN = V
SSA
. ADC
calibrated at T = 25C.
Symbol Parameter Conditions Min Typ
[2]
Max Unit
V
IA
analog input
voltage
[3]
0- V
DDA
V
C
ia
analog input
capacitance
12-bit mode
[4]
-4- pF
16-bit mode
[4]
-8- pF
f
clk(ADC)
ADC clock
frequency
<tbd> 24 MHz
f
s
sampling
frequency
- - 1.0 Msamples/s
E
D
differential
linearity error
[1][5]
- <tbd> - LSB
E
L(adj)
integral
non-linearity
V
DDA
= V
REFP
= 1.8 V
[1][6]
- <tbd> - LSB
V
DDA
= V
REFP
= 3.6 V - <tbd> - LSB
E
O
offset error calibration enabled
[1][7]
- <tbd> - mV
V
err(FS)
full-scale error
voltage
V
DDA
= V
REFP
= 1.8 V
[1][8]
- <tbd> LSB
V
DDA
= V
REFP
= 3.6 V - <tbd> LSB
Z
i
input
impedance
f
s
= 1.0 Msamples/s
[9][10]
<tbd> - - k