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1. General description

The LPC55S6x is an ARM Cortex-M33 based microcontroller for embedded applications.

These devices include an ARM Cortex-M33 coprocessor, CASPER Crypto/FFT engine,

PowerQuad hardware accelerator for DSP functions, up to 320 KB of on-chip SRAM, up

to 640 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption,

high-speed and full-speed USB host and device interface with crystal-less operation for

full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM,

one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer

(WWDT), nine flexible serial communication peripherals (which can be configured as a

USART, SPI, high speed SPI, I

C, or I

S interface), Programmable Logic Unit (PLU), one

16-bit 1.0 Msamples/sec ADC, comparator, and temperature sensor.

The ARM Cortex-M33 provides a security foundation, offering isolation to protect valuable

IP and data with TrustZone® technology. It simplifies the design and software

development of digital signal control systems with the integrated digital signal processing

(DSP) instructions. To support security requirements, the LPC55S6x also offers support

for secure boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug

authentication, and TBSA compliance.

2. Features and benefits

 ARM Cortex-M33 core (CPU0, r0p3):

 Running at a frequency of up to 100 MHz.

 TrustZone®, Floating Point Unit (FPU) and Memory Protection Unit (MPU).

 ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input with a selection of sources.

 Serial Wire Debug with eight breakpoints and four watch points. Includes Serial

Wire Output for enhanced debug capabilities.

 System tick timer.

 ARM Cortex-M33 co-processor (CPU1, r0p3):

 Running at a frequency of up to 100 MHz.

 The configuration of this instance does not include MPU, FPU, DSP, ETM, and

Trustzone.

 System tick timer.

LPC55S6x

32-bit Arm Cortex

-M33; M33 coprocessor, TrustZone,

PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS,

Flexcomm Interface, SDIO, 32-bit counter/ timers,

SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,

Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG

Rev. 1.0 — 26 February 2019 Product data sheet

Summary of content (123 pages)

PAGE 1
LPC55S6x 32-bit Arm Cortex®-M33; M33 coprocessor, TrustZone, PowerQuad, CASPER, 320 KB SRAM; 640 KB flash, USB HS, Flexcomm Interface, SDIO, 32-bit counter/ timers, SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC, Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG Rev. 1.0 — 26 February 2019 Product data sheet 1. General description The LPC55S6x is an ARM Cortex-M33 based microcontroller for embedded applications.
PAGE 2
LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller  CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC).  PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP functions with support of SDK software API faster execution of ARM CMSIS instruction set.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller options are available to each Flexcomm Interface, including a shared fractional baud-rate generator, and time-out feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I2S.  I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support high-speed Mode (3.4 Mbit/s) as a slave.  USB 2.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller  One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and match registers). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 captures/matches, 16 events, and 32 states.  32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller      LPC55S6x Product data sheet  The Micro-Tick Timer running from the watchdog oscillator, and the Real-Time Clock (RTC) running from the 32.768 kHz clock, can be used to wake-up the device from sleep and deep-sleep modes.  Power-On Reset (POR).  Brown-Out Detectors (BOD) for VBAT_DCDC with separate thresholds for forced reset. Operating from internal DC-DC converter. Single power supply 1.8 V to 3.6 V.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC55S69JBD100 HLQFP100 plastic low profile quad flat package; 100 leads; body 14  14  0.5mm pitch SOT1570-3 LPC55S66JBD100 HLQFP100 plastic low profile quad flat package; 100 leads; body 14  14  0.5mm pitch SOT1570-3 LPC55S69JEV98 VFBGA98 thin fine-pitch ball grid array package; 98 balls; body 7‘ 7‘ 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 4. Marking Terminal 1 index area n 1 Terminal 1 index area Fig 1. aaa-025721 aaa-011231 HLQFP100 package marking Fig 2. VFBGA98 package marking The LPC55S6x VFBGA98 package has the following top-side marking: • • • • First line: LPC55S6x Second line: JEV98 Third line: xxxxxxxx Fourth line: xxxyywwx1 – yyww: Date code with yy = year and ww = week.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 5. Block diagram )6 86% +6 86% EXV EXV &5<67$/ &/.,1 &/.287 9'' 567BQ /[ 'HEXJ ,QWHUIDFH '0$ '0$ 6',2 86% )6 +RVW 'HYLFH 3+< +DVK $(6 86% +6 +RVW 'HYLFH 3+< 3R5 %R' )52 3// &ORFNV 3RZHU FRQWURO '& '& &RQYHUWHU /'2V V\VWHP IXQFWLRQV &RGH $UP &RUWH[ 0 &38 6\VWHP &RGH 6\VWHP $UP $50 &RUWH[ 0 &38 &RUWH[ 0 &DVSHU 3RZHUTXDG FR SURFHVVRUV 'HEXJ ,QWHUIDFH &RSURFHVVRU LQWHUIDFH ZLWK PDWK IXQFWLR
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 6. Pinning information 6.1 Pin description Table 4 shows the pin functions available on each pin, and for each package. These functions are selectable using the IOCON control registers. Some functions, such as ADC or comparator inputs, are available only on specific pins when digital functions are disabled on those pins. By default, the GPIO function is selected except on pins PIO0_11 an PIO0_12, which are the serial wire debug pins.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_0/ ACMP0_A [4] Z Function # 54 Description Type L12 Reset state [1] 100 pin HLQFP Symbol Pin description 98 pin VFBGA Table 3. I/O; 0 AI 1 PIO0_0/ACMP0_A — General-purpose digital input/output pin. Comparator 0, input A if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin. R — Reserved. I/O 2 FC3_SCK — Flexcomm 3: USART, SPI, or I2S clock.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_2/ TRST [2] Function # 81 Description Type B11 Reset state [1] 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PD I/O 0 PIO0_2 — General-purpose digital input/output pin. In boundary scan mode: TRST (Test Reset). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MISO function.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 Function # 86 Type E7 Description Reset state [1] PIO0_4/ TMS 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PIO0_4 — General-purpose digital input/output pin. In boundary scan mode: TMS (Test Mode Select). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SSEL0 function. 1 R — Reserved. I/O 2 FC4_SCK — Flexcomm 4: USART, SPI, or I2S clock.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 Function # 89 Type B7 Description Reset state [1] PIO0_6/ TDO 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PIO0_6 — General-purpose digital input/output pin. In boundary scan mode: TDO (Test Data Out). Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SCK function. I/O 1 FC3_SCK — Flexcomm 3: USART, SPI, or I2S clock.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_9/ ACMP0_B [4] Z Function # 55 Description Type L13 Reset state [1] 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. I/O; 0 AI PIO0_9/ACMP0_B — General-purpose digital input/output pin. Comparator 0, input B if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin. I/O 1 FC3_SSEL2 — Flexcomm 3: SPI slave select 2. O SD0_POW_EN — SD/MMC 0 card power enable.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_11/ ADC0_9 [4] Function # 13 Description Type F1 Reset state [1] 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PD I/O; 0 AI PIO0_11/ADC0_9 — General-purpose digital input/output pin. ADC input channel 9 if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [3] Z I/O 0 Function # 71 Type C12 Description Reset state [1] PIO0_13 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PIO0_13 — General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SDA function. I/O 1 FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I 2 UTICK_CAP0 — Micro-tick timer capture input 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_15/ ADC0_2 [4] Z Function # 22 Description Type L2 Reset state [1] 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. I/O; 0 AI PIO0_15/ADC0_2 — General-purpose digital input/output pin. ADC input channel 2 if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin. I/O 1 FC6_CTS_SDA_SSEL0 — Flexcomm 6: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_18/ ACMP0_C [4] Z Function # 56 Description Type H9 Reset state [1] 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. I/O; 0 AI PIO0_18/ACMP0_C — General-purpose digital input/output pin. Comparator 0, input C if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin. I/O 1 FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO0_20 — General-purpose digital input/output pin. I/O 1 FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O 2 CTIMER1_MAT1 — 32-bit CTimer1 match output 1. I 3 CTIMER_INP15 — Capture input to CTIMER input multiplexers. I 4 SCT0_GPI2 — Pin input 2 to SCTimer/PWM. 5 R — Reserved. 6 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2][8] Z I/O 0 PIO0_22 — General-purpose digital input/output pin. I/O 1 FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. I 2 UTICK_CAP1 — Micro-tick timer capture input 1. I 3 CTIMER_INP15 — Capture input to CTIMER input multiplexers. O 4 SCT0_OUT3 — SCTimer/PWM output 3. 5 R — Reserved. 6 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO0_25 — General-purpose digital input/output pin. I/O 1 FC0_TXD_SCL_MISO_WS — Flexcomm 0: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. I/O 2 SD0_D[1] — SD/MMC 0 data 1. I 3 CTIMER_INP9 — Capture input to CTIMER input multiplexers. I 4 SCT0_GPI1 — Pin input 1 to SCTimer/PWM. 5 R — Reserved. 6 R — Reserved. 7 R — Reserved. 8 R — Reserved. 9 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO0_27 — General-purpose digital input/output pin. I/O 1 FC2_TXD_SCL_MISO_WS — Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. Function # 27 Type N2 Description Reset state [1] PIO0_27 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. 2 R — Reserved. O 3 CTIMER3_MAT2 — 32-bit CTimer3 match output 2.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 Function # 92 Type H8 Description Reset state [1] PIO0_29 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PIO0_29 — General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the Flexcomm 0 USART RXD function. I/O 1 FC0_RXD_SDA_MOSI_DATA — Flexcomm 0: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. I/O 2 SD1_D[2] — SD/MMC 1 data 2.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO0_31/ ADC0_3 [4] Z Function # 23 Description Type L1 Reset state [1] 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. I/O; 0 AI PIO0_31/ADC0_3 — General-purpose digital input/output pin. ADC input channel 3 if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin. I/O 1 FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2][8] Z I/O 0 Function # 59 Type G11 Description Reset state [1] PIO1_1/ WAKEUP 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PIO1_1 — General-purpose digital input/output pin. This pin can trigger a wake-up from deep power-down mode. WAKEUP pin can be configured as rising or falling edge Remark: In ISP mode, this pin is set to the High Speed SPI SSEL1 function (Flexcomm 10) I/O 1 2 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2][8] Z I/O 0 Function # 62 Type G13 Description Reset state [1] PIO1_3 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. PIO1_3 — General-purpose digital input/output pin. Remark: In ISP mode, this pin is set to the High Speed SPI MISO function (Flexcomm 10). O PIO1_4 PIO1_5 PIO1_6 PIO1_7 B2 M5 H5 J5 LPC55S6x Product data sheet 1 31 5 9 [2] [2] [2] Z Z Z Z R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller PIO1_8/ ADC0_4 [4] Z I/O; 0 AI PIO1_8/ADC0_4 — General-purpose digital input/output pin. ADC input channel 4 if the DIGIMODE bit is set to 0 and ANAMODE is set to 1 in the IOCON register for this pin. I/O 1 FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O 2 SD0_CLK — SD/MMC 0 card clock. 3 R — Reserved. 4 SCT0_OUT1 — SCTimer/PWM output 1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2][8] Z I/O 0 Function # 93 Type G6 Description Reset state [1] PIO1_11 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. 1 PIO1_12 F12 67 [2][8] Z PIO1_13 B3 2 Z FC1_TXD_SCL_MISO_WS — Flexcomm 1: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. I 3 CTIMER_INP5 — Capture input to CTIMER input multiplexers.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 Function # 82 Type B6 Description Reset state [1] PIO1_15 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. 1 R — Reserved. I 2 UTICK_CAP3 — Micro-tick timer capture input 3. I 3 CTIMER_INP7 — Capture input to CTIMER input multiplexers. I/O 4 FC5_RTS_SCL_SSEL1 — Flexcomm 5: USART request-to-send, I2C clock, SPI slave select 1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO1_18 — General-purpose digital input/output pin. This pin can trigger a wake-up from deep power-down mode. O O O PIO1_19/ ACMPVREF H13 58 [4] Z Function # 64 Type G9 Description Reset state [1] PIO1_18/ WAKUP 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. 1 SD1_POW_EN — SD/MMC 1 card power enable. 2 R — Reserved. 3 R — Reserved. 4 SCT0_OUT5 — SCTimer/PWM output 5.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO1_21 — General-purpose digital input/output pin. I/O 1 FC7_CTS_SDA_SSEL0 — Flexcomm 7: USART clear-to-send, I2C data I/O, SPI Slave Select 0. O Function # 30 Type M7 Description Reset state [1] PIO1_21 100 pin HLQFP Symbol Pin description …continued 98 pin VFBGA Table 3. 2 R — Reserved. 3 CTIMER3_MAT2 — 32-bit CTimer3 match output 2. 4 R — Reserved. I/O 5 O PIO1_22 M8 41 [2] Z 6 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO1_25 — General-purpose digital input/output pin. I/O 1 FC2_TXD_SCL_MISO_WS — Flexcomm 2: USART transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S word-select/frame. O SCT0_OUT2 — SCTimer/PWM output 2. PIO1_26 E13 68 Z 2 I/O 3 SD1_D[0] — SD/MMC 1 data 0. I 4 UTICK_CAP0 — Micro-tick timer capture input 0. 5 R — Reserved. 6 R — Reserved. 7 PLU_CLKIN — PLU clock input. 8 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [2] Z I/O 0 PIO1_28 — General-purpose digital input/output pin. I/O 1 FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock. I/O 2 SD0_D[5] — SD/MMC 0 data 5. I 3 CTIMER_INP2 — Capture input to CTIMER input multiplexers. 4 R — Reserved. 5 R — Reserved. 6 R — Reserved. 7 PLU_INPUT3 — PLU input 3. 8 R — Reserved. I PIO1_29 G8 80 [2][8] Z I/O 0 PIO1_29 — General-purpose digital input/output pin.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 91 [2] Z I/O 0 PIO1_31 — General-purpose digital input/output pin. I/O 1 MCLK — MCLK input or output for I2S. O 2 SD1_CLK — SD/MMC 1 card clock. O 3 CTIMER0_MAT2 — 32-bit CTimer0 match output 2. O 4 SCT0_OUT6 — SCTimer/PWM output 6. 5 R — Reserved. 6 R — Reserved. 7 PLU_INPUT0 — PLU input 0. 8 R — Reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 3. Pin description …continued Reset state [1] Type VSS_DCDC N12, M12 46, 47 - - VSS_PMU M11 - - - Star ground connection is managed to PCB ground plane. VSSA H2 19 - - Analog ground. XTAL32K_N J12 53 - - RTC oscillator output. XTAL32K_P J13 52 XTAL32M_N M3 28 [7] XTAL32M_P N3 29 [7] Function # 100 pin HLQFP Description 98 pin VFBGA Symbol Star ground connection is managed to PCB ground plane.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 6.1.1 Termination of unused pins Table 4 shows how to terminate pins that are not used in the application. In many cases, unused pins should be connected externally or configured correctly by software to minimize the overall power consumption of the part. Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 6.1.3 Using Internal DC-DC converter Fig 4. Using internal DC-DC converter LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M33 includes three AHB-Lite buses, one system bus and the I-code and D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is dedicated for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.8 System Tick timer (SysTick) The ARM Cortex-M33 core include a system tick timer (SysTick) that is intended to generate a dedicated SYSTICK exception. The clock source for the SysTick can be the system clock or the SYSTICK clock. 7.9 On-chip static RAM The LPC55S6x support up to 320 KB SRAM with separate bus master access for higher throughput and individual power control for low-power operation. 7.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.12 Protected Flash Region (PFR) The protected flash region is available to configure secure boot, debug authentication, read UUID, store PUF in key store area, and user defined fields available for specific data storage. 7.13 Memory mapping 7.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [1] The size shown for peripherals spaces indicates the space allocated in the memory map, not the actual space used by the peripheral or memory. [2] Selected areas of secure regions may be marked as non-secure callable. See . 7.17 Links to specific memory map descriptions and tables: • Section 7.18 “Memory map overview” • Section 7.19 “APB peripherals” • Section 7.20 “AHB peripherals” 7.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.19 APB peripherals Table 8 provides details of the addresses for APB peripherals. APB peripherals have both secure and non-secure access possibilities. Table 8. APB peripherals memory map APB Non-secure Secure Peripheral bridge base address base address 0 1 0x4000 0000 0x5000 0000 Syscon. 0x4000 1000 0x5000 1000 IOCON. Pin function selection and pin control setup.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.20 AHB peripherals Table 9 provides details of the addresses for AHB peripherals. AHB peripherals have both secure and non-secure access possibilities. Table 9. AHB peripheral memory map AHB Non-secure Secure Peripheral port base address base address 8 9 10 11 0x4008 2000 0x5008 2000 DMA0 registers. 0x4008 4000 0x5008 4000 FS USB Device registers. 0x4008 5000 0x5008 5000 SCTimer/PWM.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller entire voltage and temperature range. The FRO 12 MHz oscillator provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. • 32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 65% accuracy over the entire voltage and temperature range. Internal low power oscillator (FRO 1 MHz).
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 10. Clocking diagram signal name descriptions Name Description main_clk The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source selection are shown in Figure 5. mclk_in The MCLK input function, when it is connected to a pin by selecting it in the IOCON block. pll0_clk The output of the PLL0. The PLL0 and its source selection is shown in Figure 5. pll1_clk The output of the PLL1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.22 Power control The LPC55S6x support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be adjusted for power consumption. In addition, there are four special modes of processor power reduction with different peripherals running: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode which can be activated by the power mode configure API. 7.22.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller All SRAM, logic state, and registers maintain their internal states. All SRAM instances that are not configured to enter in ‘retention state’ will stay in active state. 7.22.4 Deep power-down mode In deep power-down mode, power is shut off to the entire chip except for the RTC power domain, the RESET pin, 4 Wake-up pins, and the OT Timer if enabled. Clock sources such as FRO 32 KHz, and the 32.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.24 Pin interrupt/pattern engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used in conjunction with software to create complex state machines based on pin inputs.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Features • • • • • • • USB2.0 full-speed device controller. Supports ten physical (five logical) endpoints including one control endpoint. Single and double-buffering supported. Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. Supports wake-up from Deep-sleep mode on USB activity and remote wake-up. Supports SoftConnect. Link Power Management (LPM) supported. 7.25.1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.25.2.2 USB1 host controller The host controller enables high speed data exchange with USB devices attached to the bus. It consists of register interface and serial interface engine. The register interface complies with the Enhanced Host Controller Interface (EHCI) specification Features • EHCI compliant. • Two downstream ports. • Supports per-port power switching. 7.25.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Features • Support standard, Fast-mode, and Fast-mode Plus (specific I2C pins) with data rates of up to 1 Mbit/s. • • • • • Support high-speed slave mode with data rates of up to 3.4 Mbit/s (specific I2C pins). • • • • 10-bit addressing supported with software assist. Independent Master, Slave, and Monitor functions. Supports both Multi-master and Multi-master with Slave functions. Multiple I2C slave addresses supported in hardware.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller • In synchronous slave mode, wakes up the part from deep-sleep and deep-sleep2 modes. • Special operating mode allows operation at up to 9600 baud using the 32.768 kHz RTC oscillator as the UART clock. This mode can be used while the device is in deep-sleep and can wake-up the device when a character is received. • USART transmit and receive functions work with the system DMA controller.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.25.4 High-speed SPI serial I/O controller 7.25.4.1 Features • Master and slave operation. • Maximum data rates of Mbit/s at tbd V  VDD  tbd V in master and slave mode for SPI functions. • Data frames of 4 to 16 bits supported directly. Larger frames supported by software. • The SPI function supports separate transmit and receive FIFOs with eight entries each.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller • Counter or timer operation. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • The timer and prescaler may be configured to be cleared on a designated capture event.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.27.2.1 Features • The SCTimer/PWM Supports: – Eight inputs. – Ten outputs. – Sixteen match/capture registers. – Sixteen events. – Thirty two states. • Counter/timer features: – Each SCTimer/PWM is configurable as two 16-bit counters or one 32-bit counter. – Counters clocked by system clock or selected input. – Configurable number of match and capture registers. Up to sixteen match and capture registers total. – Sixteen events.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.27.3 Windowed WatchDog Timer (WWDT) The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state. When enabled, a watchdog reset is generated if the user program fails to feed (reload) the Watchdog within a predetermined amount of time. 7.27.3.1 Features • Internally resets chip if not reloaded during the programmable time-out period.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller • RTC alarm and high-resolution/wake-up timer time-out each generate independent interrupt requests that go to one NVIC channel. Either time-out can wake up the part from any of the low power modes, including deep power-down. • Eight 32-bit general purpose registers can retain data in deep power-down or in the event of a power failure, provided there is battery backup. 7.27.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.28 Digital peripherals 7.28.1 DMA controller The DMA controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional DMA transfers for a single source and destination. Two identical DMA controllers are provided on the LPC55S6x.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller • Any of the eight selected PLU outputs can be enabled to contribute to an asynchronous wake-up or an interrupt request from sleep and deep-sleep modes. 7.28.3 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 7.28.3.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller • Fifteen command buffers allow independent options selection and channel sequence scanning. • Automatic compare for less-than, greater-than, within range, or out-of-range with "store on true" and "repeat until true" options. • Two independent result FIFOs each contains 16 entries. Each FIFO has configurable watermark and overflow detection. • Interrupt, DMA, or polled operation. • Linearity and gain offset calibration logic. 7.29.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.29.3 Temperature sensor The temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a Complement To Absolute Temperature (VCTAT) voltage. The output voltage varies inversely with device temperature with an absolute accuracy of better than C over the full temperature range ( C to C). The temperature sensor is only approximately linear with a slight curvature.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.30.2.1 Features • Performs SHA-1 and SHA-2(256) based hashing. • Used with HMAC to support a challenge/response or to validate a message. 7.30.3 PUF The PUF controller on the LPC55S6x provides generation and secure storage for keys without storing the key. The PUF controller provides a unique key per device and exists in that device based on the unique characteristics of PUF SRAM.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.30.5 PRINCE On-the-fly encryption/decryption LPC55S6x devices offer support for on-the-fly encryption of date being written to flash and decryption of encrypted on-chip flash data during read using the PRINCE encryption algorithm. Compared to AES, PRINCE is fast as it can decrypt and encrypt in one clock cycle. Also, it does not need extra SRAM to copy data. It operates on a block-size of 64 bits with an 128-bit key.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 8. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD Parameter Conditions [2] Main IO supply Min Max Unit -0.3 3.96 V -0.3 3.96 V VBAT_DCDC Supply of DCDC output stage. DCDC core supply (references and regulation stages) [2] VBAT_PMU Analog supply [2] -0.3 3.96 V VDD_PMU Analog supply for Core. DCDC output set to 1.1 V by default [2] -0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 11. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 10. Static characteristics 10.1 General operating conditions Table 14. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit fclk clock frequency internal CPU/system clock - - 100 MHz fclk clock frequency For USB high-speed device and 60 - 100 MHz 12 - 100 MHz 1.8 - 3.6 V VBAT_DCDC Supply of DCDC output stage.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 10.2 CoreMark data Table 15. CoreMark score Tamb = 25C, VBAT_DCDC = 3.0 V Parameter Conditions Typ Unit ARM Cortex-M33 (CPU0) in active mode; ARM Cortex-M33 (CPU1) in sleep mode CoreMark score CoreMark score CoreMark code executed from SRAMX; CCLK = 12 MHz [1][2][3] 3.8 (Iterations/s) / MHz CCLK = 48 MHz [1][2][3] 3.8 (Iterations/s) / MHz CCLK = 96 MHz [1][2][3] 3.8 (Iterations/s) / MHz [1][2][3][4] 3.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 10.3 Power consumption Table 16. Static characteristics: Power consumption in active and sleep modes Tamb = 40 C to +105 C, unless otherwise specified. VBAT_DCDC = 3.0 V Symbol Parameter Conditions Min Typ[1] Max Unit ARM Cortex-M33 (CPU0) in active mode; ARM Cortex-M33 (CPU1) in sleep mode IDD IDD supply current supply current CoreMark code executed from SRAMX; flash powered down CCLK = 12 MHz [2][3][4][5] - 1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 16. Static characteristics: Power consumption in active and sleep modes Tamb = 40 C to +105 C, unless otherwise specified. VBAT_DCDC = 3.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 18. Static characteristics: ADC Power consumption Tamb = 40 C to +105 C, unless otherwise specified.0.985 V  VREFP  VDDA V; 1.8 V  VDDA  3.6 V. Symbol IDDA IDD(VREFP) [1] Parameter analog supply current supply current on pin VREFP Conditions Min Typ[1] Max Unit ADC on; sampling a single channel at ADC clock frequency - 0.7 - mA ADC in low power mode; PWRSEL = 0 - 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller RTC input grounded. Fig 12. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD Table 20 shows the typical peripheral power consumption measured on a typical sample at Tamb = 25 °C and VDD = 3.3V.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 20. Typical peripheral power consumption VDD = 3.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller LPC55S6x Product data sheet [1] Turn off the peripheral when the configuration is done. [2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a higher frequency. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 10.4 Pin characteristics Table 21. Static characteristics: pin characteristics Tamb = 40 C to +105 C, unless otherwise specified. 1.8 V  VDD  3.6 V unless otherwise specified. Values tested in production unless otherwise specified.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 21. Static characteristics: pin characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. 1.8 V  VDD  3.6 V unless otherwise specified. Values tested in production unless otherwise specified. Symbol Parameter VIL LOW-level input voltage Vhys hysteresis voltage ILI input leakage current IOL LOW-level output current LPC55S6x Product data sheet Min Typ[1] Max Unit 1.8 V  VDD < 2.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 21. Static characteristics: pin characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. 1.8 V  VDD  3.6 V unless otherwise specified. Values tested in production unless otherwise specified.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 10.4.1 Electrical pin characteristics Conditions: VDD = 1.8 V; on pins to . Conditions: VDD = 3.3 V; on pins to . Fig 14. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins. Fig 15.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins. Fig 16. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins. Fig 17.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Conditions: VDD = 1.8V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins. Fig 18. Typical pull-down current IPD versus input voltage VI LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 22. Flash characteristics Tamb = 40 C to +105 C, unless otherwise specified.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [1] Simulated data. [2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between 80 % and 20 % of the full output signal level. [3] The slew rate is configured in the IOCON block the SLEW bit. See the LPC55S6x user manual. [4] CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level. 11.3 Wake-up process Table 24.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.4 PLL0 Table 25. PLL0 lock times and current Tamb = 40 C to +105 C, unless otherwise specified.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 26.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.5 PLL1 Table 27. PLL1 lock times and current Tamb = 40 C to +105 C, unless otherwise specified.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 28.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.8 FRO (32 KHz) Table 31. Dynamic characteristic: FRO Tamb = 40 C to +105 C; 1.8 V  VBAT_DCDC  3.6 V. Symbol Parameter Conditions Min Typ[1] Max Unit fosc(RC) FRO clock frequency - 32.11 32 33.42 KHz [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.9 RTC oscillator See Section 13.4 for connecting the RTC oscillator to an external clock source.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.11 I2S-bus interface Table 34. Dynamic characteristics: I2S-bus interface pins [1][4] Tamb = 40 C to 105 C; VBAT_DCDC = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50% level of the rising or falling edge.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Tcy(clk) tf tr I2Sx_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_RX_SDA tsu(D) th(D) I2Sx_WS aaa-026799 tv(Q) Fig 20. I2S-bus timing (master) Tcy(clk) tf tr I2Sx_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_RX_SDA tsu(D) th(D) I2Sx_WS tsu(D) th(D) aaa-026800 Fig 21. I2S-bus timing (slave) LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.12 SPI interface (Flexcomm Interfaces 0 - 7) The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode is Mbit/s, and the maximum supported bit rate for SPI slave mode is Mbit/s. Table 35.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MISO (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VAL
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MISO (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MOSI (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MOSI (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VAL
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.13 High-Speed SPI interface (Flexcomm Interface 10) The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode is Mbit/s, and the maximum supported bit rate for SPI slave mode is Mbit/s. Table 36.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MISO (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VAL
PAGE 98
LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MISO (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MOSI (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MOSI (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VAL
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.14 USART interface The actual USART bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master and slave synchronous mode is 10 Mbit/s. Table 37. USART dynamic characteristics[1] Tamb = 40 C to 105 C; VDD = 1.8 V to 3.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 11.15 SD/MMC and SDIO Table 38. Dynamic characteristics: SD/MMC and SDIO Tamb = 40 C to +105 C, VDD = 1.8 V to 3.6 V; CL = 10 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns for SD_DATn and SD_CMD pins. Simulated values in high-speed mode. Not tested in production.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 12. Analog characteristics 12.1 BODVBAT Table 40. BOD static characteristics Tamb = 25 C; based on characterization; not tested in production. Please refer to UM11126 for further details. Symbol Parameter Vth reset threshold voltage LPC55S6x Product data sheet Conditions Min Typ Max Unit - 1.00 - V - 1.10 - V - 1.20 - V - 1.30 - V - 1.40 - V - 1.50 - V - 1.60 - V - 1.65 - V - 1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 12.2 16-bit ADC characteristics Table 41. 16-bit ADC static characteristics Tamb = 40 C to +105 C; VDD = 1.8 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA. ADC calibrated at T = 25C. Symbol Parameter Conditions Min Typ Max Unit [2] VIA analog input voltage Cia analog input capacitance [3] 0 - VDDA V 12-bit mode [4] - 4 - pF 16-bit mode [4] - 8 - pF 24 MHz - - 1.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 28. 16-bit ADC characteristics 12.2.1 ADC input impedance Figure 29 shows the ADC input impedance. In this figure: • ADCx represents slow ADC input channels 6 to 11. • ADCy represents fast ADC input channels 0 to 5.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller • R1 and Rsw are the switch-on resistance on the ADC input channel. • If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through Rsw to the sampling capacitor (Cia). • If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through R1 + Rsw to the sampling capacitor (Cia). • Typical values, R1 = 487 , Rsw = 278  • See Table 21 for Cio. • See Table 41 for Cia.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller [1] Measured over matrix samples. [2] Measured for samples over process corners. Fig 30. LLS fit of the temperature sensor output voltage graph Table 44. Comparator characteristics Tamb = 40 C to +105 C unless noted otherwise; VDD = 1.8 V to 3.6 V. Symbol Parameter Conditions Min Typ[1] Max Unit Static characteristics IDD supply current Low Power Mode; Tamb = 25 °C - 2.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Table 44. Comparator characteristics …continued Tamb = 40 C to +105 C unless noted otherwise; VDD = 1.8 V to 3.6 V. Symbol Parameter Conditions Min Typ[1] Max Unit tdelay propagation delay time Low Power Mode negative input = VBAT_DCDC/2 V_overdrive = 10 mV - ns 1150 6000 V_overdrive = 50 mV - 550 - ns V_overdrive = max - 280 500 ns propagation delay time Low Power Mode negative input = VBAT_DCDC - 0.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 13. Application information 13.1 Standard I/O pin configuration Figure 31 shows the possible pin modes for standard I/O pins: • • • • • Digital output driver: enabled/disabled. Digital input: Pull-up enabled/disabled. Digital input: Pull-down enabled/disabled. Digital input: Repeater mode enabled/disabled. Z mode; High impedance (no cross-bar currents for floating inputs). The default configuration for standard I/O pins is Z mode.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller external loads connected to the pin. I/O pins also contribute to the dynamic power consumption when the pins are switching because the VDD supply provides the current to charge and discharge all internal and external capacitive loads connected to the pin in addition to powering the I/O circuitry.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Although CParasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. Therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 14. Package outline Fig 33. HLQFP100 Package outline LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Fig 34. VFBGA98 Package outline LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 15. Soldering Fig 35. HLQFP100 Soldering footprint part 1 LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Fig 36. HLQFP100 Soldering footprint part 2 LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Fig 37. HLQFP100 Soldering footprint part 3 LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Fig 38. VFBGA98 Soldering footprint part 1 LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Fig 39. VFBGA98 Soldering footprint part 2 LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller Fig 40. VFBGA98 Soldering footprint part 3 LPC55S6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 16. Abbreviations Table 45.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 17. Revision history Table 46. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC55S6x v1.0 20190225 - LPC55S6x Product data sheet Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 26 February 2019 - © NXP Semiconductors N.V. 2019. All rights reserved.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s).
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 20. Contents 1 2 3 3.1 4 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.21.1 7.21.2 7.21.3 7.21.4 7.22 7.22.1 7.22.2 7.22.3 7.22.4 7.23 7.23.1 7.24 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . .
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LPC55S6x NXP Semiconductors 32-bit ARM Cortex-M33 microcontroller 7.30.7 7.31 7.32 8 9 10 10.1 10.2 10.3 10.4 10.4.1 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 DICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Debug Mailbox and Authentication . . . . . . . . . 66 Emulation and debugging . . . . . . . . . . . . . . . . 66 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 67 Thermal characteristics. . . . . . . . . . . . . . . . . .