Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 89 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
Conditions: V
DD
= 3.3 V; T
amb
= 25 °C; active mode; all peripherals disabled; BOD disabled;
Measured with IAR ver 8.22.2. Optimization level 3, optimized for time ON.
12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,
and 180 MHz: FRO enabled; PLL enabled.
CoreMark score from SRAMX: SRAM0 is powered.
Fig 13. Typical CoreMark score ((iterations/s)/MHz) vs. Frequency (MHz) from SRAMX
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