Datasheet
LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 88 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
10. Static characteristics
10.1 General operating conditions
[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.
[2] Attempting to program below 2.7 V will result in unpredictable results and the part might enter an unrecoverable state.
10.2 CoreMark data
[1] Clock source FRO. PLL disabled.
[2] Clock source 12 MHz FRO. PLL enabled.
[3] Characterized through bench measurements using typical samples.
[4] Compiler settings: IAR C/C++ Compiler for Arm ver 8.22.2, optimization level 3, optimized for time on.
[5] SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered.
Table 12. General operating conditions
T
amb
=
40
C to +105
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
f
clk
CPU clock frequency - - 180 MHz
CPU clock frequency For USB high-speed device and
host operations
60 - 180 MHz
CPU clock frequency For USB full-speed device and host
operations
12 - 180 MHz
V
DD
supply voltage (core
and external rail)
1.71 - 3.6 V
For OTP programming only
[2]
2.7 - 3.6 V
For USB operation only 3.0 - 3.6 V
V
DDA
analog supply voltage 1.71 - 3.6 V
V
BAT
battery supply voltage 1.71 - 3.6 V
V
refp
ADC positive reference
voltage
V
DDA
2 V 2.0 - V
DDA
V
V
DDA
< 2 V V
DDA
-V
DDA
V
RTC oscillator pins
V
i(rtcx)
32.768 kHz oscillator
input voltage
on pin RTCXIN -0.5 - +3.6 V
V
o(rtcx)
32.768 kHz oscillator
output voltage
on pin RTCXOUT -0.5 - +3.6 V
V
i(xtal)
crystal input voltage on pin XTALIN 0.5 - 1.95 V
V
o(xtal)
crystal output voltage on pin XTALOUT 0.5 - 1.95 V
Table 13. CoreMark score
T
amb
=25
C, V
DD
= 3.3V
Parameter Conditions Typical Unit
ARM Cortex-M4 in active mode
CoreMark score CoreMark code executed from SRAMX;
CCLK = 12 MHz
[1][3][4][5]
3.38 (Iterations/s) / MHz
CCLK = 96 MHz
[1][3][4][5]
3.38 (Iterations/s) / MHz
CCLK = 180 MHz
[2][3][4][5]
3.38 (Iterations/s) / MHz