Datasheet

Product data sheet Rev. 1.8 — 22 June 2018 73 of 168

NXP Semiconductors

LPC540xx

32-bit ARM Cortex-M4 microcontroller

7.14.8.2 SPI serial I/O controller

Features

• Maximum data rates of 48 Mbit/s in master mode and 14 Mbit/s in slave mode for SPI

functions. (Flexcomm Interface 0-9).

• Maximum data rates of 50 Mbit/s in master mode and 50 Mbit/s in slave mode for SPI

functions (Flexcomm Interface10).

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or

DMA set-up.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Four Slave Select input/outputs with selectable polarity and flexible usage.

• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any

enabled interrupt.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

7.14.8.3 I

C-bus interface

The I

C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example, an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I

C is a multi-master bus and

can be controlled by more than one bus master connected to it.

Features

• All I2Cs support standard, Fast-mode, and Fast-mode Plus with data rates of up to

1Mbit/s.

• All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I

C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I

C-bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

• Activity on the I2C in slave mode allows wake-up from deep-sleep mode on any

enabled interrupt.