Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 72 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
• Supports DMA access.
• Provides XIP (execute in place) feature to execute code directly from serial flash.
7.14.5 CAN Flexible Data (CAN FD) interface
The LPC540xx contains two CAN FD interfaces, CAN FD 1 and CAN FD 2.
7.14.5.1 Features
• Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1.
• CAN FD with up to 64 data bytes supported.
• CAN Error Logging.
• AUTOSAR support.
• SAE J1939 support.
• Improved acceptance filtering.
7.14.6 DMIC subsystem
7.14.6.1 Features
• Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2
buses.
• Flexible decimation.
• 16 entry FIFO for each channel.
• DC blocking or unaltered DC bias can be selected.
• Data can be transferred using DMA from deep-sleep mode without waking up the
CPU, then automatically returning to deep-sleep mode.
• Data can be streamed directly to I
2
S on Flexcomm Interface 7.
7.14.7 Smart card interface
7.14.7.1 Features
• Two DMA supported ISO 7816 Smart Card Interfaces.
• Both asynchronous protocols, T = 0 and T = 1 are supported.
7.14.8 Flexcomm Interface serial communication
7.14.8.1 Features
• USART with asynchronous operation or synchronous master or slave operation.
• SPI master or slave, with up to 4 slave selects.
• I
2
C, including separate master, slave, and monitor functions.
• Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface 7.
• Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I
2
C
function does not use the FIFO.