Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 63 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
7.10.5 Clock Generation
Fig 11. LPC540xx clock generation
000
001
010
pll_clk
fro_hf
main_clk
usb_pll_clk
011
audio_pll_clk
ADC CLOCK
DIVIDER
ADCCLKDIV
CPU CLOCK
DIVIDER
to CPU, AHB bus,
Sync APB
AHBCLKDIV
ADC clock select
SYSTEM PLL
System PLL
settings
000
001
010
pll_clk
fro_hf
usb_pll_clk
111
“none”
USB0 CLOCK
DIVIDER
USB0CLKDIV
00
01
10
clk_in
fro_12m
(1)
(1)
wdt_clk
11
fro_hf
00
10
11
pll_clk
32k_clk
MAINCLKSELA[1:0]
(1)
(1): synchronized multiplexer,
see register descriptions for details.
ASYNCAPBCLKSELA[1:0]
MAINCLKSELB[1:0]
000
001
clk_in
fro_12m
011
32k_clk
111
“none”
SYSPLLCLKSEL[2:0]
000
001
010
fro_hf_div
fro_12
audio_pll_clk
011
mclk_in
111
“none”
DMIC CLOCK
DIVIDER
DMICCLKDIV
DMICCLKSEL[2:0]
USB0 clock select
MCLK
DIVIDER
MCLKDIV
MCLK clock select
000
001
AUDPLLCKSEL[2:0]
AUDIO PLL Settings
fro_12m
clk_in
Crystal
oscillator
Range select
SYSOSCCTRL[1:0]
clk_in
EMC ClOCK
DIVIDER
to EMC
(function
clock)
aaa-029067
00
01
fro_12m
main_clk
audio_pll_clk
fc6_fclk
to Async APB
000
001
fro_hf_div
audio_pll_clk
Audio PLL
USB PLL
USB PLL
settings
fro_hf_div
USB1 clock select
000
001
010
pll_clk
main_clk
usb_pll_clk
111
“none”
USB1 CLOCK
DIVIDER
to USB1 PHY
USB1CLKDIV
to ADC
to USB0
to DMIC
subsystem
to MCLK pin
(output)
111
“none”
111
“none”
USB1CLKSEL[2:0]
111
“none”
10
11
xtalin
xtalout
Main clock select A
PLL clock select
pll_clk
Main clock select B
EMCCLKDIV
FRO Clock
Divider
FROHFCLKDIV
fro_hf
clk_in
usb_pll_clk
Audio clock select
audio_pll_clk
APB clock select B
ADCCLKSEL[2:0]
(FS USB)
USB0CLKSEL[2:0]
DMIC clock select
000
001
010
100
SDIO CLOCK
DIVIDER
SDIOCLKDIV
SDIO clock select
011
to SDIO
(function clock)
111
pll_clk
main_clk
usb_pll_clk
fro_hf
audio_pll_clk
“none”
SDIOCLKSEL[2:0]
MCLKCLKSEL[1:0]
main_clk
wdt_in
100
101
01
“none”