Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 50 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
PIO4_31 - - 114 -
[2]
PU; Z I/O PIO4_31 — General-purpose digital input/output pin.
I ENET_RX_CLK — Ethernet Receive Clock (MII interface)
or Ethernet Reference Clock (RMII interface).
I/O SD_D[6] — SD/MMC data 6.
O CT3_MAT1 — Match output 1 from Timer 3.
I/O FC4_SCK — Flexcomm 4: USART or SPI clock.
R — Reserved.
I/O EMC_D[26] — External Memory interface data [26].
PIO5_0 - - 122 -
[2]
PU; Z I/O PIO5_0 — General-purpose digital input/output pin.
I ENET_RX_DV — Ethernet receive data valid.
I/O SD_D[7] — SD/MMC data 7.
O CT3_MAT2 — Match output 2 from Timer 3.
I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver,
I2C data I/O, SPI master-out/slave-in data.
R — Reserved.
I/O EMC_D[27] — External Memory interface data [27].
PIO5_1 - - 126 -
[2]
PU; Z I/O PIO5_1 — General-purpose digital input/output pin.
I ENET_CRS — Ethernet Carrier Sense (MII interface) or
Ethernet
Carrier Sense/Data Valid (RMII interface).
O SD_VOLT[0] — SD/MMC card regulator voltage control [0].
O CT3_MAT3 — Match output 3 from Timer 3.
I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter,
I2C clock, SPI master-in/slave-out data.
R — Reserved.
I/O EMC_D[28] — External Memory interface data [28].
PIO5_2 - - 202 -
[2]
PU; Z I/O PIO5_2 — General-purpose digital input/output pin.
I ENET_COL — Ethernet Collision detect (MII interface).
O SD_VOLT[1] — SD/MMC card regulator voltage control [1].
I CT3_CAP0 — Capture input 0 to Timer 3.
I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART
clear-to-send, I2C data I/O, SPI Slave Select 0.
R — Reserved.
I/O EMC_D[29] — External Memory interface data [29].
Table 4. Pin description
…continued
Symbol
100-pin, TFBGA 180-pin, TFBGA 208-pin, LQFP 100-pin, LQFP Reset state
[1]
[9]
Type
Description