Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 135 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.23 SD/MMC and SDIO
Table 49. Dynamic characteristics: SD/MMC and SDIO
T
amb
=  40  C to +105  C, V
DD
= 2.7 V to 3.6 V; C
L
= 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY
register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns
for SD_DATn and SD_CMD pins. Simulated values in high-speed mode.
Symbol Parameter Conditions Min Typ Max Unit
f
clk
clock frequency on pin SD_CLK; data transfer mode - - 50 MHz
t
su(D)
data input set-up time on pins SD_DATn as inputs
CCLK  100 MHz 14.4 - - ns
CCLK > 100 MHz 14.4 - - ns
on pins SD_CMD as inputs
CCLK  100 MHz 14.4 - - ns
CCLK > 100 MHz 14.4 - - ns
t
h(D)
data input hold time on pins SD_DATn as inputs
CCLK  100 MHz 1.5 - - ns
CCLK > 100 MHz 1.5 - - ns
on pins SD_CMD as inputs
CCLK  100 MHz 1.5 - - ns
CCLK > 100 MHz 1.5 - - ns
t
v(Q)
data output valid time on pins SD_DATn as outputs
CCLK  100 MHz 1.9 - 3.5 ns
CCLK > 100 MHz 1.9 - 3.5 ns
on pins SD_CMD as outputs
CCLK  100 MHz 1.9 - 3.5 ns
CCLK > 100 MHz 1.9 - 3.5 ns
Fig 40. SD/MMC and SDIO timing
002aag204
SD_CLK
SD_DATn (O)
SD_DATn (I)
t
d(QV)
t
h(D)
t
su(D)
T
cy(clk)
t
h(Q)
SD_CMD (O)
SD_CMD (I)