Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 134 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
t
h
data input hold time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
CCLK  100 MHz 1.2 - 0 ns
CCLK > 100 MHz 1.2 - 0 ns
t
v(Q)
data output valid
time
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2]
CCLK  100 MHz 10.0 - 18.2 ns
CCLK > 100 MHz 10.0 - 18.2 ns
Table 48. Dynamic characteristics: Ethernet
T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V. C
L
= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.
Symbol Parameter Conditions Min Typ Max Unit
Fig 38. Ethernet RMII timing
Fig 39. Ethernet MII timing
aaa-025108
t
h
ENET_RX_CLK
ENET_TX_EN
ENET_TXDn
ENET_RXDn
ENET_RX_DV
t
su
t
v(Q)
aaa-025109
t
h
ENET_RX_CLK
ENET_TX_EN
ENET_TX_CLK
ENET_RX_ER
ENET_TXDn
ENET_RXDn
ENET_RX_DV
t
su
t
v(Q)