Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 133 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11. 21
11.22 Ethernet AVB
Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply
with the IEEE standard 802.3.
Fig 37. Differential data-to-EOP transition skew and EOP width
002aab561
T
PERIOD
differential
data lines
crossover point
source EOP width: t
FEOPT
receiver EOP width: t
EOPR1
, t
EOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × T
PERIOD
+ t
FDEOP
Table 48. Dynamic characteristics: Ethernet
T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V. C
L
= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.
Symbol Parameter Conditions Min Typ Max Unit
RMII mode
f
clk
clock frequency for ENET_RX_CLK
[1]
- - 50.0 MHz

clk
clock duty cycle
[1]
45.0 - 55.0 %
t
su
data input set-up
time
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
CCLK  100 MHz 4.4 - - ns
CCLK > 100 MHz 4.4 - - ns
t
h
data input hold time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
CCLK  100 MHz 1.3 - 0 ns
CCLK > 100 MHz 1.3 - 0 ns
t
v(Q)
data output valid
time
for ENET_TXDn, ENET_TX_EN
[1][2]
CCLK  100 MHz 9.9 - 17.3 ns
CCLK > 100 MHz 9.9 - 17.3 ns
MII mode
f
clk
clock frequency for ENET_TX_CLK
[1]
- - 25.0 MHz

clk
clock duty cycle
[1]
45.0 - 55.0 %
f
clk
clock frequency for ENET_RX_CLK
[1]
- - 25.0 MHz

clk
clock duty cycle
[1]
45.0 - 55.0 %
t
su
data input set-up
time
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
CCLK  100 MHz 4.7 - - ns
CCLK > 100 MHz 4.7 - - ns