Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 131 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.18 USART interface
The actual USART bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for USART
master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART
slave synchronous mode is 12.5 Mbit/s.
[1] Based on characterization; not tested in production.
Table 45. USART dynamic characteristics
[1]
T
amb
=  40  C to 105  C; V
DD
= 1.71 V to 3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ Max Unit
USART master (in synchronous mode) 1.71 V  VDD  2.7 V
t
su(D)
data input set-up time CCLK  100 MHz 21.2 - - ns
CCLK > 100 MHz 19.7 - - ns
t
h(D)
data input hold time CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
t
v(Q)
data output valid time CCLK  100 MHz 0 - 4.9 ns
CCLK > 100 MHz 0 - 4.5 ns
USART slave (in synchronous mode)1.71 V  VDD  2.7 V
t
su(D)
data input set-up time CCLK  100 MHz 1.7 - - ns
CCLK > 100 MHz 1.5 - - ns
t
h(D)
data input hold time CCLK  100 MHz 1.2 - - ns
CCLK > 100 MHz 1.4 - - ns
t
v(Q)
data output valid time CCLK  100 MHz 20.2 - 39.5 ns
CCLK > 100 MHz 19.3 - 37.7 ns
USART master (in synchronous mode) 2.7 V  VDD  3.6 V
t
su(D)
data input set-up time CCLK  100 MHz 20.5 - - ns
CCLK > 100 MHz 18.9 - - ns
t
h(D)
data input hold time CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
t
v(Q)
data output valid time CCLK  100 MHz 1.5 - 3.6 ns
CCLK > 100 MHz 1.3 - 3.2 ns
USART slave (in synchronous mode) 2.7 V  VDD  3.6 V
t
su(D)
data input set-up time CCLK  100 MHz 1.2 - - ns
CCLK > 100 MHz 1 - - ns
t
h(D)
data input hold time CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
t
v(Q)
data output valid time CCLK  100 MHz 15.2 - 26.1 ns
CCLK > 100 MHz 14.3 - 24.2 ns