Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 129 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.15 SPIFI
The actual SPIFI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPIFI mode is
100 Mbit/s.
[1] Based on simulation; not tested in production.
Table 42. Dynamic characteristics: SPIFI
[1]
T
amb
=  40  C to 105  C; V
DD
= 1.71 V to 3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ Max Unit
SPIFI 1.71 V  VDD  2.7 V
t
DS
data set-up time CCLK  100 MHz 4 - - ns
CCLK > 100 MHz 4 - - ns
t
DH
data hold time CCLK  100 MHz 6.4 - - ns
CCLK > 100 MHz 6.6 - - ns
t
v(Q)
data output valid time CCLK  100 MHz 5.7 - 13.7 ns
CCLK > 100 MHz 5.7 - 13.7 ns
SPIFI 2.7 V  VDD  3.6 V
t
DS
data set-up time CCLK  100 MHz 4 - - ns
CCLK > 100 MHz 4 - - ns
t
DH
data hold time CCLK  100 MHz 3.5 - - ns
CCLK > 100 MHz 3.6 - - ns
t
v(Q)
data output valid time CCLK  100 MHz 3.3 - 11.5 ns
CCLK > 100 MHz 3.3 - 11.5 ns
In mode 0, MODE3 bit (23) in SPIFI CTRL register is set to '0' (default). The SPIFI drives SCK low
after the rising edge at which the last bit of each command is captured, and keeps it LOW while CS
is HIGH.
Fig 34. SPIFI control register (Mode 0)
SPIFI_SCK
SPIFI data out
SPIFI data in
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
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