Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 126 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.14 SPI interfaces (Flexcomm Interface 10)
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 50 Mbit/s, and the maximum supported bit rate for SPI slave mode is 50 Mbit/s.
[1] Based on characterization; not tested in production.
Table 41. SPI dynamic characteristics
[1]
T
amb
=  40  C to 105  C; 1.71 V  V
DD
 3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew
= 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the
rising or falling edge.
Symbol Parameter Conditions Min Typ Max Unit
SPI master
t
DS
data set-up time 0 - - ns
t
DH
data hold time 10.0 - - ns
t
v(Q)
data output valid time 0.8 - 10.0 ns
SPI slave
t
DS
data set-up time 1.2 - - ns
t
DH
data hold time 10.0 - - ns
t
v(Q)
data output valid time 4.28 - 10.0 ns