Datasheet
LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 123 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.13 SPI interfaces (Flexcomm Interface 0-9)
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s.
[1] Based on characterization; not tested in production.
Table 40. SPI dynamic characteristics
[1]
T
amb
=
40
C to 105
C; 1.71 V
V
DD
3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ Max Unit
SPI master 1.71 V V
DD
2.7 V
t
DS
data set-up time CCLK 100 MHz 2.2 - - ns
CCLK > 100 MHz 1.9 - - ns
t
DH
data hold time CCLK 100 MHz 6.3 - - ns
CCLK > 100 MHz 6.7 - - ns
t
v(Q)
data output valid time CCLK 100 MHz 2.6 - 5.0 ns
CCLK > 100 MHz 0.3 - 4.7 ns
SPI slave 1.71 V V
DD
2.7 V
t
DS
data set-up time CCLK 100 MHz 1.1 - - ns
CCLK > 100 MHz 0.9 - - ns
t
DH
data hold time CCLK 100 MHz 2.1 - - ns
CCLK > 100 MHz 2.2 - - ns
t
v(Q)
data output valid time CCLK 100 MHz 18.8 - 37.0 ns
CCLK > 100 MHz 18.0 - 36.0 ns
SPI master 2.7 V V
DD
3.6 V
t
DS
data set-up time CCLK 100 MHz 2.4 - - ns
CCLK > 100 MHz 2.2 - - ns
t
DH
data hold time CCLK 100 MHz 4.2 - - ns
CCLK > 100 MHz 4.5 - - ns
t
v(Q)
data output valid time CCLK 100 MHz 1.8 - 4.6 ns
CCLK > 100 MHz 1.7 - 4.0 ns
SPI slave 2.7 V V
DD
3.6 V
t
DS
data set-up time CCLK 100 MHz 1.2 - - ns
CCLK > 100 MHz 1.0 - - ns
t
DH
data hold time CCLK 100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
t
v(Q)
data output valid time CCLK 100 MHz 14 - 23.9 ns
CCLK > 100 MHz 13.3 - 22.2 ns