Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 121 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[1] Based on characterization; not tested in production.
[2] Clock Divider register (DIV) = 0x0.
[3] Typical ratings are not guaranteed.
[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section
in the I
2
S chapter (UM11060) to calculate clock and sample rates.
[5] Based on simulation. Not tested in production.
Master; 2.7 V  VDD  3.6 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK  100 MHz 21.4 - 30.4 ns
CCLK > 100 MHz 20.6 - 28.7 ns
on pin I2Sx_WS
CCLK  100 MHz 21.1 - 29 ns
CCLK > 100 MHz 20.3 - 28.3 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 1.3 - - ns
CCLK > 100 MHz 1.0 - - ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 2.9 - - ns
CCLK > 100 MHz 3.3 - - ns
Slave; 2.7 V  VDD  3.6 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK  100 MHz 13.8 - 23.6 ns
CCLK > 100 MHz 13 - 21.9 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 4.7 - - ns
CCLK > 100 MHz 4.2 - - ns
on pin I2Sx_WS
CCLK  100 MHz 0.9 - - ns
CCLK > 100 MHz 0.7 - - ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
on pin I2Sx_WS
CCLK  100 MHz 1.5 - - ns
CCLK > 100 MHz 1.3 - - ns
Table 39. Dynamic characteristics: I
2
S-bus interface pins
[1][4]
T
amb
=  40  C to 105  C; V
DD
= 1.71 V to 3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ
[3]
Max Unit