Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 120 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.12 I
2
S-bus interface
Table 39. Dynamic characteristics: I
2
S-bus interface pins
[1][4]
T
amb
=  40  C to 105  C; V
DD
= 1.71 V to 3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ
[3]
Max Unit
Common to master and slave
t
WH
pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK
[5]
CCLK  100 MHz (T
cyc
/2) -1 - (T
cyc
/2) +1 ns
CCLK > 100 MHz (T
cyc
/2) -1 - (T
cyc
/2) +1 ns
t
WL
pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK
[5]
CCLK  100 MHz (T
cyc
/2) -1 - (T
cyc
/2) +1 ns
CCLK > 100 MHz (T
cyc
/2) -1 - (T
cyc
/2) +1 ns
Master; 1.71 V  VDD  2.7 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK  100 MHz 26.0 - 40.3 ns
CCLK > 100 MHz 25.0 - 39.0 ns
on pin I2Sx_WS
CCLK  100 MHz 26.0 - 41.0 ns
CCLK > 100 MHz 25.0 - 39.6 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 6.1 - - ns
CCLK > 100 MHz 6.4 - - ns
Slave; 1.71 V  VDD  2.7 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK  100 MHz 18.8 - 37.1 ns
CCLK > 100 MHz 18.0 - 35.5 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 4.8 - - ns
CCLK > 100 MHz 4.4 - - ns
on pin I2Sx_WS
CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
on pin I2Sx_WS
CCLK  100 MHz 3.2 - - ns
CCLK > 100 MHz 3.2 - - ns