Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 114 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.5 USB PLL (PLL1)
[1] Data based on characterization results, not tested in production.
[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.
[1] Data based on simulation, not tested in production.
[2] Excluding under- and overshoot which may occur when the PLL is not in lock.
[3] Actual jitter dependent on amplitude and spectrum of substrate noise.
[4] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.
11.6 Audio PLL (PLL2)
[1] Data based on characterization results, not tested in production.
[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.
Table 30. PLL1 lock times and current
T
amb
=  40  C to +105  C, unless otherwise specified. V
DD
= 1.71 V to 3.6 V
Symbol Parameter Conditions Min Typ Max Unit
PLL1 configuration: input frequency 12 MHz; output frequency 48 MHz
t
lock(PLL1)
PLL1 lock time
[1]
-7.4- s
I
DD(PLL1)
PLL1 current When locked
[1][2]
- 260 - A
Table 31. Dynamic characteristics of the PLL1
[1]
Symbol Parameter Conditions Min Typ Max Unit
Reference clock input
F
in
input frequency 1 - 25 MHz
Clock output
f
o
output frequency for PLL1 clkout
output
[2]
9.75 - 160 MHz
d
o
output duty cycle for PLL1 clkout
output
45 - 55 %
f
CCO
CCO frequency 156 - 320 MHz
Dynamic parameters at f
out
= f
CCO
= 320 MHz; standard bandwidth settings
J
pp-period
peak-to-peak, period
jitter
f
ref
= 4 MHz
[3][4]
- - 300 ps
Table 32. PLL2 lock times and current
T
amb
=  40  C to +105  C, unless otherwise specified. V
DD
= 1.71 V to 3.6 V
Symbol Parameter Conditions Min Typ Max Unit
PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz
t
lock(PLL2)
PLL2 lock time
[1]
--96 s
I
DD(PLL2)
PLL2 current when locked
[1][2]
--2.0mA
PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz
t
lock(PLL2)
PLL2 lock time
[1]
- - 108 s
I
DD(PLL2)
PLL2 current when locked
[1][2]
--1.6mA