Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 113 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.4 System PLL (PLL0)
[1] Data based on characterization results, not tested in production.
[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.
[1] Data based on characterization results, not tested in production.
[2] Excluding under- and overshoot which may occur when the PLL is not in lock.
[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion
means lock output is HIGH.
[4] Actual jitter dependent on amplitude and spectrum of substrate noise.
[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.
Table 28. PLL lock times and current
T
amb
=  40  C to +105  C, unless otherwise specified. V
DD
= 1.71 V to 3.6 V
Symbol Parameter Conditions Min Typ Max Unit
PLL0 configuration: input frequency 12 MHz; output frequency 100 MHz
t
lock(PLL0)
PLL0 lock time
[1]
96 s
I
DD(PLL0)
PLL0 current when locked
[1][2]
--2.0mA
PLL0 configuration: input frequency 32 kHz; output frequency 100 MHz
t
lock(PLL0)
PLL0 lock time
[1]
- - 108 s
I
DD(PLL0)
PLL0 current when locked
[1][2]
--1.6mA
Table 29. Dynamic characteristics of the PLL0
[1]
Symbol Parameter Conditions Min Typ Max Unit
Reference clock input
F
in
input frequency 32.768 kHz - 25 MHz
Clock output
f
o
output frequency for PLL0 clkout output
[2]
4.3 - 550 MHz
d
o
output duty cycle for PLL0 clkout output 46 - 54 %
f
CCO
CCO frequency 275 - 550 MHz
Lock detector output

lock(PFD)
PFD lock criterion
[3]
124 ns
Dynamic parameters at f
out
= f
CCO
= 540 MHz; standard bandwidth settings
J
rms-interval
RMS interval jitter f
ref
= 10 MHz
[4][5]
-1530 ps
J
pp-period
peak-to-peak, period jitter f
ref
= 10 MHz
[4][5]
-4080 ps