Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 112 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0.
Table 27. Dynamic characteristics: Dynamic external memory interface programmable clock delays (CMDDLY,
FBCLKDLY)
T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V.Values guaranteed by design. t
cmddly
is programmable delay value for EMC
command outputs in command delayed mode; t
fbdly
is programmable delay value for the feedback clock that controls input
data sampling.
Symbols Parameter Five bit value for each delay in EMCDLYCTL
[1]
Min Typ Max Unit
t
cmddly
, t
fbdly
delay time b00000 0.41 0.66 0.77 ns
b00001 0.52 0.85 1.03 ns
b00010 0.69 1.11 1.3 ns
b00011 0.8 1.3 1.56 ns
b00100 0.95 1.53 1.77 ns
b00101 1.06 1.72 2.03 ns
b00110 1.23 1.98 2.3 ns
b00111 1.34 2.17 2.56 ns
b01000 1.45 2.3 2.67 ns
b01001 1.56 2.49 2.93 ns
b01010 1.73 2.75 3.2 ns
b01011 1.84 2.94 3.46 ns
b01100 1.99 3.17 3.67 ns
b01101 2.1 3.36 3.93 ns
b01110 2.27 3.62 4.2 ns
b01111 2.38 3.81 4.46 ns
b10000 2.45 3.86 4.46 ns
b10001 2.56 4.05 4.72 ns
b10010 2.73 4.31 4.99 ns
b10011 2.84 4.5 5.25 ns
b10100 2.99 4.73 5.46 ns
b10101 3.1 4.92 5.72 ns
b10110 3.27 5.18 5.99 ns
b10111 3.38 5.37 6.25 ns
b11000 3.49 5.5 6.36 ns
b11001 3.6 5.69 6.62 ns
b11010 3.77 5.95 6.89 ns
b11011 3.88 6.14 7.15 ns
b11100 4.03 6.37 7.36 ns
b11101 4.14 6.56 7.62 ns
b11110 4.31 6.82 7.89 ns
b11111 4.42 7.01 8.15 ns