Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 110 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.
[2] See Table 27
for internal programmable delay.
Table 26. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
[2]
C
L
= 20 pF balanced loading on all pins, T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB. Values based on simulation. t
cmddly
is programmable delay value for EMC
command outputs in command delayed mode; t
fbdly
is programmable delay value for the feedback clock that controls input
data sampling.
Symbol Parameter Min Typ Max Unit
For RD = 1
Common to read and write cycles
T
cy(clk)
clock cycle time
[1]
10 - - ns
t
d(SV)
chip select valid delay time - - t
cmddly
+ 4.9 ns
t
h(S)
chip select hold time t
cmddly
+ 2.4 - - ns
t
d(RASV)
row address strobe valid
delay time
--t
cmddly
+ 5.4 ns
t
h(RAS)
row address strobe hold
time
t
cmddly
+ 2.5 - - ns
t
d(CASV)
column address strobe valid
delay time
--t
cmddly
+ 5.6 ns
t
h(CAS)
column address strobe hold
time
t
cmddly
+ 2.6 - - ns
t
d(WV)
write valid delay time - - t
cmddly
+ 6.3 ns
t
h(W)
write hold time t
cmddly
+ 3.1 - - ns
t
d(AV)
address valid delay time - - t
cmddly
+ 6.1 ns
t
h(A)
address hold time t
cmddly
+ 2.4 - - ns
Read cycle parameters
t
su(D)
data input set-up time 0.5 - - ns
t
h(D)
data input hold time 2.1 - - ns
Write cycle parameters
t
d(QV)
data output valid delay time - - 9.3 ns
t
h(Q)
data output hold time 2.4 - - ns