Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 107 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[2] T
cy(clk)
= 1/EMC_CLK (see UM11060 LPC540xx manual).
[3] Latest of address valid, EMC_CSx
LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[4] After End Of Read (EOR): Earliest of EMC_CSx
HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx
HIGH, EMC_BLSx HIGH (PB = 1).
[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060
LPC540xx manual).
Fig 23. External static memory read/write access (PB = 0)
RD
1
RD
5
RD
2
WR
2
WR
9
WR
12
WR
10
WR
11
RD
5b
RD
5a
RD
6
WR
8
WR
1
EOR
EOW
RD
7
RD
4
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
EMC_Dx
aaa-026103
RD
8