Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 106 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[1] Parameters are shown as RD
n
or WD
n
in Figure 23 as indicated in the Conditions column.
t
h(D)
data input hold time RD
6
[2][4]
5.5 - - ns
t
CSHBLSH
CS HIGH to BLS HIGH
time
PB = 1
[6]
0.7 - 1.5 ns
t
CSHOEH
CS HIGH to OE HIGH
time
[2]
0.5 - 0.9 ns
t
OEHANV
OE HIGH to address
invalid time
RD
8
[2]
0.4 - 0 ns
t
deact
deactivation time RD
7
[2]
0.5 - 0.9 ns
Write cycle parameters
[2]
t
CSLAV
CS LOW to address
valid time
WR
1
0.1 - 0.5 ns
t
CSLDV
CS LOW to data valid
time
WR
2
1-2.2 ns
t
CSLWEL
CS LOW to WE LOW
time
WR
3
; PB =1
[2][6]
0.5 +
(WAITWEN + 1) 
T
cy(clk)
- (WAITWEN + 1)  T
cy(clk)
ns
t
CSLBLSL
CS LOW to BLS LOW
time
WR
4
; PB = 1
[2][6]
1.9 - 0 ns
t
WELWEH
WE LOW to WE HIGH
time
WR
5
; PB =1
[2][6]
0.1 +
(WAITWEN + 1) 
T
cy(clk)
- (WAITWEN + 1)  T
cy(clk)
ns
t
BLSLBLSH
BLS LOW to BLS
HIGH time
PB = 1
[2][6]
3.1 - 6.7 ns
t
WEHDNV
WE HIGH to data
invalid time
WR
6
; PB =1
[2][6]
1.6 + T
cy(clk)
- 2.8 + T
cy(clk)
ns
t
WEHEOW
WE HIGH to end of
write time
WR
7
; PB = 1
[2][5][6]
0.5+T
cy(clk)
- 0.8 + T
cy(clk)
ns
t
BLSHDNV
BLS HIGH to data
invalid time
PB = 1
[6]
0.8 - 0 ns
t
WEHANV
WE HIGH to address
invalid time
PB = 1
[6]
0.5 - 0.8 ns
t
deact
deactivation time WR
8
; PB = 0;
PB = 1
[2][6]
0.8 - 0 ns
t
CSLBLSL
CS LOW to BLS LOW WR
9
; PB = 0
[2][6]
1.9
+ (WAITWEN + 1)
 T
cy(clk)
- (WAITWEN + 1)  T
cy(clk)
ns
t
BLSLBLSH
BLS LOW to BLS
HIGH time
WR
10
; PB = 0
[2][6]
3.1+ (WAITWR 
WAITWEN + 1) 
T
cy(clk)
-6.7+ (WAITWR
WAITWEN + 1)  T
cy(clk)
ns
t
BLSHEOW
BLS HIGH to end of
write time
WR
11
; PB = 0
[2][5][6]
0.8
+ T
cy(clk)
-T
cy(clk)
ns
t
BLSHDNV
BLS HIGH to data
invalid time
WR12;
PB = 0
[2][6]
0.2 + T
cy(clk)
- 0.5 + T
cy(clk)
ns
Table 24. Dynamic characteristics: Static external memory interface
…continued
C
L
= 20 pF balanced loading on all pins, T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit