Datasheet

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 105 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
[1] Parameters are shown as RD
n
or WD
n
in Figure 23 as indicated in the Conditions column.
[2] T
cy(clk)
= 1/EMC_CLK (see UM11060 LPC540xx manual).
[3] Latest of address valid, EMC_CSx
LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[4] After End Of Read (EOR): Earliest of EMC_CSx
HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx
HIGH, EMC_BLSx HIGH (PB = 1).
[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060
LPC540xx manual).
t
BLSHDNV
BLS HIGH to data
invalid time
PB = 1
[6]
0.8 - 0 ns
t
WEHANV
WE HIGH to address
invalid time
PB = 1
[6]
0.6 - 0.9 ns
t
deact
deactivation time WR
8
; PB = 0;
PB = 1
[2][6]
0.8 - 0 ns
t
CSLBLSL
CS LOW to BLS LOW WR
9
; PB = 0
[2][6]
1.2
+ (WAITWEN + 1)
 T
cy(clk)
- (WAITWEN + 1)
 T
cy(clk)
ns
t
BLSLBLSH
BLS LOW to BLS
HIGH time
WR
10
; PB = 0
[2][6]
2.5
+ (WAITWR 
WAITWEN + 1) 
T
cy(clk)
-5.5
+ (WAITWR 
WAITWEN + 1) 
T
cy(clk)
ns
t
BLSHEOW
BLS HIGH to end of
write time
WR
11
; PB = 0
[2][5][6]
0.8
+ T
cy(clk)
-T
cy(clk)
ns
t
BLSHDNV
BLS HIGH to data
invalid time
WR12;
PB = 0
[2][6]
0.2 + T
cy(clk)
- 0.5 + T
cy(clk)
ns
Table 23. Dynamic characteristics: Static external memory interface …continued
C
L
= 10 pF balanced loading on all pins, T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit
Table 24. Dynamic characteristics: Static external memory interface
C
L
= 20 pF balanced loading on all pins, T
amb
=  40  C to 105  C, V
DD
= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit
Read cycle parameters
t
CSLAV
CS LOW to address
valid time
RD
1
1.2 - 1.6 ns
t
CSLOEL
CS LOW to OE LOW
time
RD
2
[2]
0.5+ T
cy(clk)

WAITOEN
-0.8+ T
cy(clk)
 WAITOEN ns
t
CSLBLSL
CS LOW to BLS LOW
time
RD
3
; PB = 1
[2][6]
2.3 - 0 ns
t
OELOEH
OE LOW to OE HIGH
time
RD
4
[2]
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
-0.3
+ (WAITRD 
WAITOEN + 1)  T
cy(clk)
ns
t
am
memory access time RD
5
[2][3]
7.9
+ (WAITRD 
WAITOEN +1) 
T
cy(clk)
-- ns