Datasheet
LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.8 — 22 June 2018 104 of 168
NXP Semiconductors
LPC540xx
32-bit ARM Cortex-M4 microcontroller
11.3 External memory interface
Table 23. Dynamic characteristics: Static external memory interface
C
L
= 10 pF balanced loading on all pins, T
amb
=
40
C to 105
C, V
DD
= 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit
Read cycle parameters
t
CSLAV
CS LOW to address
valid time
RD
1
1.2 - 1.6 ns
t
CSLOEL
CS LOW to OE LOW
time
RD
2
[2]
0.4+ T
cy(clk)
WAITOEN
-0.8+ T
cy(clk)
WAITOEN
ns
t
CSLBLSL
CS LOW to BLS LOW
time
RD
3
; PB = 1
[2][6]
1.6 - 0 ns
t
OELOEH
OE LOW to OE HIGH
time
RD
4
[2]
(WAITRD
WAITOEN + 1)
T
cy(clk)
-0.3
+ (WAITRD
WAITOEN + 1)
T
cy(clk)
ns
t
am
memory access time RD
5
[2][3]
6.7
+ (WAITRD
WAITOEN +1)
T
cy(clk)
--ns
t
h(D)
data input hold time RD
6
[2][4]
4.8 - - ns
t
CSHBLSH
CS HIGH to BLS HIGH
time
PB = 1
[6]
0.8 - 1.5 ns
t
CSHOEH
CS HIGH to OE HIGH
time
[2]
0.5 - 0.9 ns
t
OEHANV
OE HIGH to address
invalid time
[2]
0.4 - 0 ns
t
deact
deactivation time RD
7
[2]
0.5 - 0.9 ns
Write cycle parameters
t
CSLAV
CS LOW to address
valid time
WR
1
0.1 - 0.5 ns
t
CSLDV
CS LOW to data valid
time
WR
2
1.0 - 2.2 ns
t
CSLWEL
CS LOW to WE LOW
time
WR
3
; PB =1
[2][6]
0.6 - 0 ns
t
CSLBLSL
CS LOW to BLS LOW
time
WR
4
; PB = 1
[2][6]
1.2 - 0 ns
t
WELWEH
WE LOW to WE HIGH
time
WR
5
; PB =1
[2][6]
(WAITWR
WAITWEN + 1)
T
cy(clk)
-0.1
+ (WAITWR
WAITWEN + 1)
T
cy(clk)
ns
t
BLSLBLSH
BLS LOW to BLS
HIGH time
PB = 1
[2][6]
2.5 - 5.5 ns
t
WEHDNV
WE HIGH to data
invalid time
WR
6
; PB =1
[2][6]
1.6 - 2.9 ns
t
WEHEOW
WE HIGH to end of
write time
WR
7
; PB = 1
[2][5][6]
0.6 - 0.9 ns