Datasheet

NXP Semiconductors
KTPF4210EPEVBUG
KITPF4210EPEVB evaluation board
KTPF4210EPEVBUG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User guide Rev. 1.0 — 8 February 2018
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Figure 2. Input/output terminal blocks
Table 4. Connector definitions
Connector Function Pin definition
J34 Mini USB connector Pin 1 - VBUS
Pin 2 - D−
Pin 3 - D+
Pin 4 - NC
Pin 5 - GND
Chassis - GND
J35 BDM connector Pin 1 - BKGD_JM60
Pin 2 - GND
Pin 3 - NC
Pin 4 - RST_JM60
Pin 5 - NC
Pin 6 - USB_PWR
J36 Programmer connector Pin 1 - VDDOTPIN (8.5 V boost output)
Pin 2 - 3V3 (3.3 V LDO output)
Pin 3 - GND
Pin 4 - MCU_SCL (I
2
C clock signal)
Pin 5 - MCU_SDA (I
2
C data signal)
Pin 6 - PWRON (controls the PWRON on the target device)
Pin 7 - GPIO 1 (general purpose GPIO)
Pin 8 - GPIO 2 (general purpose GPIO)
J42 Debug Port 1 Debugging connector for future development tools
J43 Debug Port 2 Debugging connector for future development tools
J44 Debug Port 3 Debugging connector for future development tools