Datasheet

NXP Semiconductors

KTPF4210EPEVBUG

KITPF4210EPEVB evaluation board

User guide Rev. 1.0 — 8 February 2018

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Figure 1. Default jumper configuration

Table 2. Jumper definitions

Jumper Default Description

J1-J7 Closed Buck regulators input power path isolation

Short these jumpers to allow SWxIN to be powered from the SWVIN supply

J9 Closed SWBST regulator input power path isolation

Short this jumper to allow SWBSTIN to be powered from the SWVIN supply

J17 5-6 VDDOTP supply selector

• 1-2: Connect VDDOTP to the OTP Boost output (VDDOTPIN) for OTP

programming

• 3-4: Connect VDDOTP to GND to power up from OTP/TBB sequence

• 5-6: Connect VDDOTP to VCOREDIG to power up from default power-up

sequence

J20 1-2 Coin cell selector

• 1-2: Enables BAT1 as the main coin cell supply

• 2-3: Enables BAT2 as the main coin cell supply

J40 Closed Shorts PVIN and SWVIN

Allows supply isolation to provide more accurate efficiency readings on the

switching supplies

J41 Open Shorts SWVIN to VIN

Allows one to isolate or connect the PF4210 logic input supply to SWVIN net.

(debugging option)

J27 Closed Shorts PVIN to VIN

Allows one to isolate or connect the PF4210 logic input supply to PVIN net.

(debugging option)

J22 2-3 PF4210 input logic supply selector

• 1-2: Connects PF4210 VIN terminal to the 3.3 V external LDO regulator for

debugging purposes

• 2-3: Connects PF420 VIN terminal to the main input supply

J26 Open Short to hold PWRON pin low

J24 Open Short to pull STANDBY to VSNVS voltage supply

J39 1-2 Control interface input supply selector

• 1-2: Enables PVIN node as the input supply source for the control interface

• 2-3: Enables USB power as the input supply source for the control

interface