Datasheet
NXP Semiconductors
KTPF4210EPEVBUG
KITPF4210EPEVB evaluation board
KTPF4210EPEVBUG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User guide Rev. 1.0 — 8 February 2018
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4.2 Device features
Table 1. Device features
Device Description Features
PF4210 The PF4210 Power Management
Integrated Circuit (PMIC) provides
a highly programmable/configurable
architecture with fully integrated
power devices and minimal external
components. With up to six buck
converters, six linear regulators,
RTC supply, and coin-cell charger,
the PF4210 can provide power
for a complete system, including
applications processors, memory,
and system peripherals, in a wide
range of applications.
• Four to six buck converters, depending on configuration
– Single/Dual phase/ parallel options
– DDR termination tracking mode option
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (One Time Programmable) memory for device
configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event
detection
• I
2
C control
• Individually programmable ON, OFF, and Standby modes
MC9S08JM60 The KITPF4210EPEVB implements
a NXP MC9S08JM60 low-cost,
high-performance 8-bit HCS08
microcontroller to interface via USB
to I
2
C to control the main PMIC.
• 8-bit HCS08 Central Processing Unit (CPU)
– Up to 24 MHz internal bus (48 MHz HCS08 core)
frequency offering 2.7 to 5.5 V across temperature
range of −40 °C to +85 °C
– Support for up to 32 peripheral interrupt/reset sources
• On-chip memory
– Up to 60 K flash read/program/erase over full operating
voltage and temperature
– Up to 4 K RAM
– 256 Byte USB RAM
4.3 Board description
The KITPF4210EPEVB operates with a single power supply from 3.1 V to 4.5 V and
is controlled via USB with help of an integrated USB-I2C communication bridge. By
applying the input voltage supply, the KITPF4210EPEVB powers up according to the
default power-up sequence described in the PF4210 data sheet.
Important: If power-up sequences and configurations are to be modified, the user must
ensure that the register settings are consistent with the hardware configuration. This
is most important for the buck regulators, where the quantity, size, and value of the
inductors depend on the configuration (single/dual phase or independent mode) and the
switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by
the buck regulator in the start-up sequence. See PF4210 data sheet for details on buck
regulator setup.
4.3.1 Jumper definitions
By default, the KITPF4210EPEVB evaluation board is set to power up from the default
power-up sequence. Verify that the jumpers are placed in the right position as shown in
Figure 1. For a detailed description of the jumper functionality, see Table 2.