Datasheet

NXP Semiconductors
KTPF4210EPEVBUG
KITPF4210EPEVB evaluation board
KTPF4210EPEVBUG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User guide Rev. 1.0 — 8 February 2018
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Tables
Tab. 1. Device features ................................................. 5
Tab. 2. Jumper definitions ............................................. 6
Tab. 3. Terminal block definitions ..................................7
Tab. 4. Connector definitions .........................................8
Tab. 5. SW1A/B/C configuration chart ...........................9
Tab. 6. SW3A/B configuration chart ............................ 10
Tab. 7. LDO input supply configuration chart .............. 11
Tab. 8. LED state description ......................................12
Figures
Fig. 1. Default jumper configuration ............................. 6
Fig. 2. Input/output terminal blocks .............................. 8
Fig. 3. SW1A/B/C output configuration .........................9
Fig. 4. SW3A/B output configuration .......................... 10
Fig. 5. LDO schematic configuration .......................... 10
Fig. 6. Logic and core supplies .................................. 10
Fig. 7. Key test point locations and default voltages ... 11
Fig. 8. Power on circuit .............................................. 12
Fig. 9. PMIC status indicator ......................................12
Fig. 10. Control/programming interface ........................13
Fig. 11. Evaluation board setup ................................... 14