Datasheet

NXP Semiconductors
KTPF4210EPEVBUG
KITPF4210EPEVB evaluation board
KTPF4210EPEVBUG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User guide Rev. 1.0 — 8 February 2018
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Table 7. LDO input supply configuration chart
Input pin Input options
[1]
VIN1 Input supply for VGEN1 and VGEN2
R20 = SW4
R21 = SW2
VIN2 Input supply for VGEN3 and VGEN4
R24 = SW4
R22 = SW2
VIN3 Input supply for VGEN5 and VGEN6
R23 = VIN
R25 = SW2
VINREFDDR VREFDDR input supply
R26 = SW3A
R27 = SW3B
VDDIO VDDIO input supply
3V3 J46 = 1-2
SW2 J46 = 2-3
[1] Make sure to populate only one option per input pin to avoid shorts between various sources.
4.3.3.4 Test point definitions
All test points are clearly marked on the KITPF4210EPEVB evaluation board. Figure 7
shows the location of various test points.
Figure 7. Key test point locations and default voltages
4.3.4 Miscellaneous components
4.3.4.1 Power on push button
A footprint for a normally open, momentary push-button is provided at the PWRON
terminal to allow a momentary low state by pressing the push button. J47 allows isolation
of the PWRON terminal from the MCU GPIO controlling this pin.