Datasheet

NXP Semiconductors
UM11193
KITFS85AEEVM evaluation board
UM11193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 2.1 — 30 January 2019
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impacts the functionality of the device. It is key to understand how OTP parameters can
be programmed, the interaction with mirror registers and the FS85 SoC.
The OTP related operations can be performed either in Emulation mode, where the
product uses a given configuration as long as power supply is not switched Off or from
OTP fuse content that is valid even after a power down/power up sequence.
4.2.1 OTP and mirrors registers
There are two OTP blocks in the device. One is for the main section, and the other for
the fail-safe. During configuration, each of them are using dedicated sectors. The OTP
configuration scheme is shown in Figure 9 (same implementation for main and fail-safe).
The device can be fused three times using mirror registers. The user can first load the
mirror register content with the desired contents, then decide either to use the device
in Emulation mode or to burn the next sector. The first sector to be burned is S1, the
second S1bis and the third S1ter. FlexGUI automatically manages the next sector to be
burned. It is not possible to revert back to the previous sector. When the user reaches
the sector S1ter, there no other possibility for burn, however emulation mode is still
available.
Note: When device is operating in Emulation mode using configuration from mirror
registers, few parameters must be overwritten by SPI/I2C. This concerns regulator
TSD behaviors; VPRE slew rate high-side and low-side VBOOST slew rate. See
Section 8.4.10 "TestMode:Mirrors_Main and TestMode:Mirrors_Failsafe" for additional
details.
a
a
a
-
0
3
1
9
6
5
SPI/I2C
primary CONFIG
images CONFIG
FS85 SOC
configuration
mirror
register
S1 - CONFIG
OTP fuse
configuration
S1 - CONFIG
S1bis - CONFIG
S1ter - CONFIG
Figure 9. OTP configuration
At boot, the content of the valid sector is loaded into the Mirror Register Sector 1. The
mirror register content is accessible from FlexGUI by using specific SPI/I2C commands.
The mirror configuration is managed by the FlexGUI, which eases the access.
4.2.2 OTP hardware implementation
To work in OTP emulation or OTP programming, it is required to start the device in
Debug mode.
Figure 10 shows the sequence to be followed to enter in Debug mode. The voltage
sequence on the kit is done using switches installed on the board, while the OTP
registers configuration is managed by the FlexGUI GUI. This is described in detail in the
following sections.