Datasheet

NXP Semiconductors
UM11193
KITFS85AEEVM evaluation board
UM11193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 2.1 — 30 January 2019
51 / 52
Tables
Tab. 1. Compensation network ......................................6
Tab. 2. Evaluation board board component
descriptions ..................................................... 10
Tab. 3. Evaluation board indicator descriptions ...........12
Tab. 4. VBAT Phoenix connector (J1) .........................13
Tab. 5. BUCK1/BUCK2 connector (J14) ..................... 14
Tab. 6. VBOOST/BUCK3 connector (J16) ...................14
Tab. 7. LDO1/LDO2 connector (J2) .............................14
Tab. 8. VPRE connector (J3) ...................................... 14
Tab. 9. Debug connector (J29) ....................................14
Tab. 10. Program connector (J30) ................................ 15
Tab. 11. Evaluation board test point descriptions ..........16
Tab. 12. Evaluation board jumper descriptions ............. 17
Tab. 13. SW3 .................................................................18
Tab. 14. SW2 .................................................................19
Tab. 15. SW1 .................................................................19
Tab. 16. Jumper configuration .......................................28
Tab. 17. Switch configuration ........................................ 28
Tab. 18. FS85 starting sequence example ....................32
Tab. 19. OTP burning flag status .................................. 45
Figures
Fig. 1. KITFS85AEEVM ................................................1
Fig. 2. VMONx configuration ........................................ 5
Fig. 3. VPRE compensation network ............................5
Fig. 4. BUCK1 and BUCK2 multiphase
configuration ......................................................6
Fig. 5. SPI connection to KL25Z .................................. 6
Fig. 6. J30 SPI connection ........................................... 7
Fig. 7. VDDIO selection ................................................7
Fig. 8. VDDI2C supply ..................................................7
Fig. 9. OTP configuration ............................................. 8
Fig. 10. Debug mode entry ............................................ 9
Fig. 11. OTP hardware implementation ..........................9
Fig. 12. Evaluation board featured component
locations .......................................................... 10
Fig. 13. Evaluation board indicator locations ................12
Fig. 14. Evaluation board connector locations ..............13
Fig. 15. Evaluation board test points ............................16
Fig. 16. Evaluation board jumper locations .................. 17
Fig. 17. Switch locations .............................................. 18
Fig. 18. Typical initial configuration .............................. 28
Fig. 19. OTP_conf_main_reg spreadsheet example .... 30
Fig. 20. OTP_conf_failsafe_reg spreadsheet
example ........................................................... 30
Fig. 21. OTP_conf_summary example ......................... 31
Fig. 22. OTP script generation ..................................... 31
Fig. 23. Launcher panel - bus selection ....................... 34
Fig. 24. Main panel .......................................................35
Fig. 25. Disabling device mode polling .........................36
Fig. 26. Script Editor .....................................................36
Fig. 27. Build a command ............................................ 38
Fig. 28. Send script ...................................................... 38
Fig. 29. Correct format ................................................. 38
Fig. 30. Wrong format (“//” missing in second line) .......38
Fig. 31. Register map ...................................................40
Fig. 32. Clocks ..............................................................40
Fig. 33. Regulators ....................................................... 41
Fig. 34. Measurements .................................................42
Fig. 35. Interrupt flags .................................................. 42
Fig. 36. INIT safety .......................................................43
Fig. 37. Diag safety ...................................................... 44
Fig. 38. OTP burning ....................................................45
Fig. 39. TestMode:Sequencer ...................................... 46
Fig. 40. Slot management ............................................ 46
Fig. 41. TestMode: Mirrors_Main ................................. 47
Fig. 42. TestMode: Mirrors_FailSafe ............................ 48