Datasheet

NXP Semiconductors
UM11193
KITFS85AEEVM evaluation board
UM11193 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 2.1 — 30 January 2019
32 / 52
emulation means that the user can emulate the OTP writing in the mirror register. This
allows trials before burning the OTP.
1. Configure the hardware. See Section 6 "Configuring the hardware for startup".
2. Launch the FlexGUI software.
3. Switch to Debug mode:
a. Place SW1 in TOP direction (VBAT switched On).
b. Close SW2 (WAKE1).
While in Debug mode, all regulators are turned Off.
4. Load the mirror registers to work in OTP emulation mode. See Section 8.3 "Working
with the Script editor".
5. Unplug jumper J24 1-2 to start the device with the mirror configuration setting.
a. If the mirror registers are filled (with a configuration using the Script editor), that
configuration is used in the emulation session.
b. If the mirror registers are not filled (with a configuration using the Script editor), the
currently-programmed OTP fuse configuration is used, if it exists.
c. Otherwise, the mirror registers are not filled and the OTP fuse is not burned, and
the device will not start up.
As long as initialization phase is not closed by a first good WD_Answer, the WD does
not start and regulators do not stay alive. Also, as long as Debug mode is not exited
by writing FS_STATES:[DBG_EXIT] bit to 1, the FS0B pin cannot be released.
6. Use the FlexGUI software to evaluate the device configured. See Section 8 "Using
FlexGUI".
7.2.1 Example script: Closing initialization phase, disabling FCCU monitoring
and releasing FS0B
The following script can be used to:
• Disable the WD (simple WD configuration is used here).
• Disable the FCCU monitoring.
On the hardware kit, the FCCU1 is pulled to GND and FCCU2 is pulled to VDDIO,
which is detected as error phase by default. Disabling the FCCU by SPI/I2C avoids
safety issue at startup.
• Close the initialization phase.
• Exit the Debug mode.
• Release FS0B pin. This is valid only if WD is activated in OTP.
Seven good consecutive WD answers are required to have the FLT_ERR_CNTR back
to 0. This is one of the conditions to allow FS0B release.
Table 18. FS85 starting sequence example
Step Register name Value Description
1 FS_WD_WINDOW 0x0200 WDW_WINDOWS[3:0] = 0x0 => Watchdog disabled
2 FS_NOT_WD_WINDOW 0xF50F NOT of FS_WD_WINDOW
3 FS_I_SAFE_INPUTS 0x51C6 FCCU_CFG[1:0] = 0x0 => 0x1 => Monitoring by pair
FCCU12_FLT_POL[0] = 1 => FCCU1 or 2 = 0 is a fault
4 FS_I_NOT_SAFE_INPUTS 0xAC18 NOT of FS_I_SAFE_INPUTS
5 FS_WD_ANSWER 0x5AB2 1st good WD answer (for simple WD selection in OTP)
Close the initialization phase
6 FS_STATES 0x4000 DBG_EXIT[0]=1 => Exit Debug mode