Datasheet

J11

J12

J11

J10

Input data valid

Output data valid

TCLK

TDI/TMS

TDO

Figure 8. Test Access Port timing

J14

J13

TCLK

TRST

Figure 9. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

Peripheral operating requirements and behaviors

K10 Sub-Family Data Sheet, Rev. 3, 11/2012.

Freescale Semiconductor, Inc. 25