Datasheet

IP4220CZ6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 8 July 2011 6 of 9
NXP Semiconductors
IP4220CZ6
Dual USB 2.0 integrated ESD protection
11. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
IP4220CZ6 v.5 20110708 Product data sheet - IP4220CZ6 v.4
Modifications:
• The format of this document has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 1 “Product profile”: updated
• Section 2 “Pinning information”: updated
• Section 4 “Marking”: added
• Table 4 and 6: parameters V
I/O
; V
esd
; C
I/O(n)
; V
I/O(n)
; I
L(n)
; C
d(Zener)
and V
BR(Zener)
redefined
respectively to V
I
; V
ESD
; C
(I/O-GND)
; V
I
; I
RM
; C
(zd-GND)
and V
BRzd
.
• Figure 1: updated
• Figure 2 “Package outline SOT457 (SC-74)”: updated
• Section 8.2. IP4220CZ6 spice model: deleted
• Section 10 “Soldering”: added
• Abbreviation table: deleted
• Section 12 “Legal information”: updated
IP4220CZ6 v.4 20050912 Product data sheet - IP4220CZ6 v.3
IP4220CZ6 v.3 20050712 Product data sheet - IP4220CZ6 v.2
IP4220CZ6 v.2 20050608 Product data sheet - IP4220CZ6_N v.1
IP4220CZ6_N v.1 20040917 Preliminary specification - -