Datasheet

Specifications
MIMXRT1050 EVK Board Hardware User’s Guide, User's Guide, Rev. 1, 11/2017
8 NXP Semiconductors
Figure 5. Power Control Diagram
NOTE
Power Control Diagram described in MIMXRT1050 EVK Board is true for TO1.0 For TO2.0,
DCDC_IN is expected to be powered with other domains together.
In the other word, for TO1.0 the DCDC_IN is powered with LDO (Path 1). And for TO2.0, it is
expected to be powered with DC/DC (Path 2).
For silicon TO1.0, please following above power logic as if not power the SNVS together with
DCDC_IN, the on chip DCDC module will not power up correctly.
The power rails on the board are shown in Table 5.
Table 5. Power Rails
Power Rail
MIN
(V)
TYP
(V)
MAX
(V)
Description
VDD_SOC_IN
0.925
--
1.26
Core supplies input voltage
VDD_HIGH_IN
3
3.3
3.6
VDD_HIGH_IN supply voltage
DCDC_IN
2.9¹
3.0¹
3.1¹
Power for DCDC