Datasheet

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
82 NXP Semiconductors
Electrical Characteristics
4.12.4.3 SDR50/SDR104 AC Timing
Figure 41 depicts the timing of SDR50/SDR104, and Table 52 lists the SDR50/SDR104 timing
characteristics.
Figure 41. SDR50/SDR104 Timing
Table 52. SDR50/SDR104 Interface Timing Specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency Period t
CLK
4.8 — ns
SD2 Clock Low Time t
CL
0.46 × t
CLK
0.54 × t
CLK
ns
SD3 Clock High Time t
CH
0.46 × t
CLK
0.54 × t
CLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)
SD4 uSDHC Output Delay t
OD
–3 1 ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)
SD5
uSDHC Output Delay t
OD
–1.6 0.74 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)
SD6
uSDHC Input Setup Time t
ISU
2.5 — ns
SD7
uSDHC Input Hold Time t
IH
1.5 — ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)
1
1
Data window in SDR100 mode is variable.
SD8
Card Output Data Window t
ODW
0.5 × t
CLK
—ns
Output from uSDHC to card
Input from card to uSDHC
SCK
SD4
SD3
SD5
S
D
3
SD8
SD7
SD6
SD1
SD2