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i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

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Electrical Characteristics

4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 49 shows the interface timing values. The number field in the table refers to timing

signals found in Figure 37 and Figure 38.

Table 49. Enhanced Serial Audio Interface (ESAI) Timing

ID Parameter

1,2

Symbol Expression

Min Max Condition

Unit

62 Clock cycle

SSICC

4 × T

30.0

—

i ck

63 Clock high period:

• For internal clock

• For external clock

—

2 × T

− 9.0

2 × T

—

64 Clock low period:

• For internal clock

• For external clock

—

2 × T

− 9.0

2 × T

—

65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high —

—

19.0

7.0

x ck

i ck a

66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low —

—

19.0

7.0

x ck

i ck a

67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)

high

—

19.0

9.0

x ck

i ck a

68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low

—

19.0

9.0

x ck

i ck a

69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high —

—

19.0

6.0

x ck

i ck a

70 ESAI_RX_CLK rising edge to ESAI_RX_FSout (wl) low —

—

17.0

7.0

x ck

i ck a

71 Data in setup time before ESAI_RX_CLK (serial clock in

synchronous mode) falling edge

—

12.0

19.0

—

x ck

i ck

72 Data in hold time after ESAI_RX_CLK falling edge —

—

3.5

9.0

—

x ck

i ck

73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK

falling edge

—

2.0

19.0

—

x ck

i ck a

74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK

falling edge

—

2.0

19.0

—

x ck

i ck a

75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling

edge

—

2.5

8.5

—

x ck

i ck a

78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high —

—

19.0

8.0

x ck

i ck

79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low —

—

20.0

10.0

x ck

i ck

80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)

high

—

20.0

10.0

x ck

i ck