Datasheet

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
146 NXP Semiconductors
Package Information and Contact Assignments
6.2.3 21 x 21 mm Functional Contact Assignments
Table 96 displays an alpha-sorted list of the signal assignments including power rails. The table also
includes out of reset pad state.
VDDHIGH_CAP H10, J10 Secondary supply for the 2.5 V domain
(internal regulator output—requires
capacitor if internal regulator is used)
VDDHIGH_IN H9, J9 Primary supply for the 2.5 V regulator
VDDPU_CAP H17, J17, K17, L17, M17, N17, P17 Secondary supply for the VPU and
GPU (internal regulator output—
requires capacitor if internal regulator
is used)
VDDSOC_CAP R10, T10, T13, T14, U10, U13, U14 Secondary supply for the SoC and PU
(internal regulator output—requires
capacitor if internal regulator is used)
VDDSOC_IN H16, J16, K16, L16, M16, N16, P16, R16, T16, U16 Primary supply for the SoC and PU
regulators
VDDUSB_CAP F9 Secondary supply for the 3 V domain
(internal regulator output—requires
capacitor if internal regulator is used)
ZQPAD AE17 Connect ZQPAD to an external 240Ω
1% resistor to GND. This is a reference
used during DRAM output buffer driver
calibration.
Table 96. 21 x 21 mm Functional Contact Assignments
Ball Name Ball Power Group Ball Type
Out of Reset Condition
1
Default
Mode
(Reset
Mode)
Default Function
(Signal Name)
Input/Output Value
2
BOOT_MODE0 C12 VDD_SNVS_IN GPIO ALT0 SRC_BOOT_MODE0 Input PD (100K)
BOOT_MODE1 F12 VDD_SNVS_IN GPIO ALT0 SRC_BOOT_MODE1 Input PD (100K)
CLK1_N C7 VDD_HIGH_CAP — — CLK1_N — —
CLK1_P D7 VDD_HIGH_CAP — — CLK1_P — —
CLK2_N C5 VDD_HIGH_CAP — — CLK2_N — —
CLK2_P D5 VDD_HIGH_CAP — — CLK2_P — —
CSI_CLK0M F4 NVCC_MIPI — — CSI_CLK_N — —
CSI_CLK0P F3 NVCC_MIPI — — CSI_CLK_P — —
CSI_D0M E4 NVCC_MIPI — — CSI_DATA0_N — —
CSI_D0P E3 NVCC_MIPI — — CSI_DATA0_P — —
CSI_D1M D1 NVCC_MIPI — — CSI_DATA1_N — —
Table 95. 21 x 21 mm Supplies Contact Assignment (continued)
Supply Rail Name Ball(s) Position(s) Remark