Datasheet

Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors 135
4.12.21.2.3 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
UART IrDA Mode Transmitter
Figure 96 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists
the transmit timing characteristics.
Figure 96. UART IrDA Mode Transmit Timing Diagram
UART IrDA Mode Receiver
Figure 97 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 90 lists
the receive timing characteristics.
Figure 97. UART IrDA Mode Receive Timing Diagram
Table 89. IrDA Mode Transmit Timing Parameters
ID Parameter Symbol Min Max Unit
UA3 Transmit Bit Time in IrDA mode t
TIRbit
1/F
baud_rate
1
– T
ref_clk
2
1
F
baud_rate
: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2
T
ref_clk
: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
1/F
baud_rate
+ T
ref_clk
—
UA4 Transmit IR Pulse Duration t
TIRpulse
(3/16) × (1/F
baud_rate
) – T
ref_clk
(3/16) × (1/F
baud_rate
) + T
ref_clk
—
Table 90. IrDA Mode Receive Timing Parameters
ID Parameter Symbol Min Max Unit
UA5 Receive Bit Time
1
in IrDA mode
1
The UART receiver can tolerate 1/(16 × F
baud_rate
) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 ×
F
baud_rate
).
t
RIRbit
1/F
baud_rate
2
–
1/(16 × F
baud_rate
)
2
F
baud_rate
: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
1/F
baud_rate
+
1/(16 × F
baud_rate
)
—
UA6 Receive IR Pulse Duration t
RIRpulse
1.41 μs (5/16) × (1/F
baud_rate
)—
Bit 1
Bit 2
Bit 0
Bit 4 Bit 5 Bit 6 Bit 7
UARTx_TX_DATA
(output)
Bit 3
Start
Bit
STOP
BIT
POSSIBLE
PARITY
BIT
UA3
UA3
UA3
UA3
UA4
Bit 1
Bit 2
Bit 0
Bit 4 Bit 5 Bit 6 Bit 7Bit 3
STOP
BIT
POSSIBLE
PARITY
BIT
UA5
UA5
UA5
UA5
UA6
Start
Bit
UARTx_RX_DATA
(input)