Datasheet

Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors 131
NOTE
• All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
AUDx_TXC/AUDx_RXC and/or the frame sync
AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.
• All timings are on Audiomux Pads when SSI is being used for data
transfer.
• AUDx_TXC and AUDx_RXC refer to the Transmit and Receive
sections of the SSI.
• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
• For internal Frame Sync operation using external clock, the frame sync
timing is same as that of transmit data (for example, during AC97 mode
of operation).
4.12.20.4 SSI Receiver Timing with External Clock
Figure 93 depicts the SSI receiver external clock timing and Table 85 lists the timing parameters for the
receiver timing with the external clock.
Figure 93. SSI Receiver External Clock Timing Diagram
Synchronous External Clock Operation
SS44 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns
SS45 AUDx_RXD hold after AUDx_TXC falling 2.0 — ns
SS46 AUDx_RXD rise/fall time — 6.0 ns
Table 84. SSI Transmitter Timing with External Clock (continued)
ID Parameter Min Max Unit
SS24
SS34
SS35
SS30
SS28
SS26
SS25
SS23
SS40
SS22
SS32
SS36
SS41
AUDx_TXC
(Input)
AUDx_TXFS (bl)
(Input)
AUDx_TXFS (wl)
(Input)
AUDx_RXD
(Input)