Datasheet

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
130 NXP Semiconductors
Electrical Characteristics
4.12.20.3 SSI Transmitter Timing with External Clock
Figure 92 depicts the SSI transmitter external clock timing and Table 84 lists the timing parameters for
the transmitter timing with the external clock.
Figure 92. SSI Transmitter External Clock Timing Diagram
Table 84. SSI Transmitter Timing with External Clock
ID Parameter Min Max Unit
External Clock Operation
SS22 AUDx_TXC/AUDx_RXC clock period 81.4 — ns
SS23 AUDx_TXC/AUDx_RXC clock high period 36.0 — ns
SS24 AUDx_TXC/AUDx_RXC clock rise time — 6.0 ns
SS25 AUDx_TXC/AUDx_RXC clock low period 36.0 — ns
SS26 AUDx_TXC/AUDx_RXC clock fall time — 6.0 ns
SS27 AUDx_TXC high to AUDx_TXFS (bl) high –10.0 15.0 ns
SS29 AUDx_TXC high to AUDx_TXFS (bl) low 10.0 — ns
SS31 AUDx_TXC high to AUDx_TXFS (wl) high –10.0 15.0 ns
SS33 AUDx_TXC high to AUDx_TXFS (wl) low 10.0 — ns
SS37 AUDx_TXC high to AUDx_TXD valid from high impedance — 15.0 ns
SS38 AUDx_TXC high to AUDx_TXD high/low — 15.0 ns
SS39 AUDx_TXC high to AUDx_TXD high impedance — 15.0 ns
SS45
SS33
SS24
SS26
SS25
SS23
Note: AUDx_RXD Input in Synchronous mode only
SS31
SS29
SS27
SS22
SS44
SS39
SS38
SS37
SS46
AUDx_TXC
(Input)
AUDx_TXFS (bl)
(Input)
AUDx_TXFS (wl)
(Input)
AUDx_TXD
(Output)
AUDx_RXD
(Input)