Datasheet

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
126 NXP Semiconductors
Electrical Characteristics
4.12.20 SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in Table 81.
NOTE
The terms WL and BL used in the timing diagrams and tables refer to Word
Length (WL) and Bit Length (BL).
4.12.20.1 SSI Transmitter Timing with Internal Clock
Figure 90 depicts the SSI transmitter internal clock timing and Table 82 lists the timing parameters for
the SSI transmitter internal clock.
.
Figure 90. SSI Transmitter Internal Clock Timing Diagram
Table 81. AUDMUX Port Allocation
Port Signal Nomenclature Type and Access
AUDMUX port 1 SSI 1 Internal
AUDMUX port 2 SSI 2 Internal
AUDMUX port 3 AUD3 External – AUD3 I/O
AUDMUX port 4 AUD4 External – EIM or CSPI1 I/O through IOMUXC
AUDMUX port 5 AUD5 External – EIM or SD1 I/O through IOMUXC
AUDMUX port 6 AUD6 External – EIM or DISP2 through IOMUXC
AUDMUX port 7 SSI 3 Internal
SS19
SS1
SS2
SS4
SS3
SS5
SS6
SS8
SS10
SS12
SS14
SS18
SS15
SS17
SS16
SS43
SS42
Note: AUDx_RXD input in synchronous mode only
AUDx_TXC
(Output)
AUDx_TXFS (wl)
(Output)
AUDx_TXFS (bl)
(Output)
AUDx_RXD
(Input)
AUDx_TXD
(Output)