Datasheet
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors 119
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed in Table 74; unless otherwise noted.
Table 75 lists the MediaLB 6-pin interface timing characteristics, and Figure 82 shows the MLB 6-pin
delay, setup, and hold times.
Bus Hold from MLB_CLK low t
mdzh
4—ns —
Transmitter MLBSIG (MLBDAT)
output valid from transition of
MLBCLK (low-to-high)
Tdelay — 10.75 — ns
1
The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLB_CLK.
2
MLB_CLK low/high time includes the pulse width variation.
3
The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the
final driven bit on the line must remain on the bus for t
mdzh
. Therefore, coupling must be minimized while meeting the maximum
load capacitance listed.
Table 74. MLB 1024 Fs Timing Parameters
Parameter Symbol Min Max Unit Comment
MLB_CLK Operating Frequency
1
1
The controller can shut off MLB_CLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLB_CLK.
f
mck
45.056 51.2 MHz 1024xfs at 44.0 kHz
1024xfs at 50.0 kHz
MLB_CLK rise time t
mckr
—1ns V
IL
TO V
IH
MLB_CLK fall time t
mckf
—1ns V
IH
TO V
IL
MLB_CLK low time t
mckl
6.1 — ns (see
2
)
2
MLB_CLK low/high time includes the pulse width variation.
MLB_CLK high time t
mckh
9.3 — ns —
MLB_SIG/MLB_DATA receiver input valid to
MLB_CLK falling
t
dsmcf
1—ns —
MLB_SIG/MLB_DATA receiver input hold
from MLB_CLK low
t
dhmcf
t
mdzh
—ns —
MLB_SIG/MLB_DATA output high
impedance from MLB_CLK low
t
mcfdz
0t
mckl
ns (see
3
)
3
The MediaLB driver can release the MLB_DATA/MLB_SIG line as soon as MLB_CLK is low; however, the logic state of the
final driven bit on the line must remain on the bus for t
mdzh
. Therefore, coupling must be minimized while meeting the maximum
load capacitance listed.
Bus Hold from MLB_CLK low t
mdzh
2—ns —
Transmitter MLBSIG (MLBDAT) output valid
from transition of MLBCLK (low-to-high)
Tdelay — 6 ns —
Table 73. MLB 256/512 Fs Timing Parameters (continued)
Parameter Symbol Min Max Unit Comment