Datasheet
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018
NXP Semiconductors 115
4.12.13.6 Frame Transmission Mode (Synchronized Data Flow)
Figure 78. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow)
4.12.13.7 Frame Transmission Mode (Pipelined Data Flow)
Figure 79. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)
4.12.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load
Table 70. DATA and FLAG Timing
Parameter Description 1 Mbit/s 100 Mbit/s
t
Bit, nom
Nominal bit time 1000 ns 10 ns
t
Rise, min
and t
Fall, min
Minimum allowed rise and fall time 2 ns 2 ns
t
TxToRxSkew, maxfq
Maximum skew between transmitter and receiver package pins 50 ns 0.5 ns
t
EageSepTx, min
Minimum allowed separation of signal transitions at transmitter package pins,
including all timing defects, for example, jitter and skew, inside the transmitter.
400 ns 4 ns
t
EageSepRx, min
Minimum separation of signal transitions, measured at the receiver package pins,
including all timing defects, for example, jitter and skew, inside the receiver.
350 ns 3.5 ns
Complete N-bits Frame
Complete N-bits Frame
DATA
FLAG
READY
Channel
Description
bits
P
a
y
l
o
a
d
D
a
t
a
B
i
t
s
Frame
start bit
Complete N-bits Frame Complete N-bits Frame
DATA
FLAG
READY
Channel
Description
bits
P
a
y
l
o
a
d
D
a
t
a
B
i
t
s
Frame
start bit