Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
98 NXP Semiconductors
Electrical Characteristics
4.12.10.3 Electrical Characteristics
Figure 61 depicts the sensor interface timing. IPU2_CSIx_PIX_CLK signal described here is not
generated by the IPU. Table 63 lists the sensor interface timing characteristics.
Figure 61. Sensor Interface Timing Diagram
4.12.10.4 IPU Display Interface Signal Mapping
The IPU supports a number of display output video formats. Table 64 defines the mapping of the Display
Interface Pins used during various supported video interface formats.
Table 63. Sensor Interface Timing Characteristics
ID Parameter Symbol Min Max Unit
IP1 Sensor output (pixel) clock frequency Fpck 0.01 180 MHz
IP2 Data and control setup time Tsu 2 — ns
IP3 Data and control holdup time Thd 1 — ns
— Vsync to Hsync Tv-h 1/Fpck — ns
— Vsync and Hsync pulse width Tpulse 1/Fpck — ns
— Vsync to first data Tv-d 1/Fpck — ns
Table 64. Video Signal Cross-Reference
i.MX 6Dual/6Quad LCD
Comment
1,2
Port Name
(x = 0, 1)
RGB,
Signal
Name
(General)
RGB/TV Signal Allocation (Example)
16-bit
RGB
18-bit
RGB
24 Bit
RGB
8-bit
YCrCb
3
16-bit
YCrCb
20-bit
YCrCb
IPUx_DISPx_DAT00 DAT[0] B[0] B[0] B[0] Y/C[0] C[0] C[0] —
IPUx_DISPx_DAT01 DAT[1] B[1] B[1] B[1] Y/C[1] C[1] C[1] —
IPUx_DISPx_DAT02 DAT[2] B[2] B[2] B[2] Y/C[2] C[2] C[2] —
IPUx_DISPx_DAT03 DAT[3] B[3] B[3] B[3] Y/C[3] C[3] C[3] —
IPUx_DISPx_DAT04 DAT[4] B[4] B[4] B[4] Y/C[4] C[4] C[4] —
IP3
IPUx_CSIx_DATA_EN,
IPUx_CSIx_VSYNC,
IP2
1/IP1
IPUx_CSIx_PIX_CLK
(Sensor Output)
IPUx_CSIx_HSYNC