Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
8 NXP Semiconductors
Introduction
• Support DVFS techniques for low power modes
• Use Software State Retention and Power Gating for Arm and MPE
• Support various levels of system power modes
• Use flexible clock gating control scheme
The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:
• VPU—Video Processing Unit
• IPUv3H—Image Processing Unit version 3H (2 IPUs)
• GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4
• GPU2Dv2—2D Graphics Processing Unit (BitBlt) version 2
• GPUVG—OpenVG 1.1 Graphics Processing Unit
• ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
• Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
• CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and
True and Pseudo Random Number Generator (NIST certified)
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
1.3 Signal Naming Convention
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be
used to map the signal names used in older documentation to the new standardized naming conventions.
The signal names of the i.MX6 series of products are standardized to align the signal names within the
family and across the documentation. Benefits of this standardization are as follows:
• Signal names are unique within the scope of an SoC and within the series of products
• Searches will return all occurrences of the named signal
• Signal names are consistent between i.MX 6 series products implementing the same modules
• The module instance is incorporated into the signal name