Datasheet
Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 77
81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low
5
—
—
—
—
—
—
22.0
12.0
x ck
i ck
ns
82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high —
—
—
—
—
—
19.0
9.0
x ck
i ck
ns
83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low —
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
84 ESAI_TX_CLK rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
ns
86 ESAI_TX_CLK rising edge to data out valid —
—
—
—
—
—
19.0
13.0
x ck
i ck
ns
87 ESAI_TX_CLK rising edge to data out high impedance
67
—
—
—
—
—
—
21.0
16.0
x ck
i ck
ns
89 ESAI_TX_FS input (bl, wr) setup time before
ESAI_TX_CLK falling edge
5
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
90 ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK
falling edge
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling
edge
—
—
—
—
4.0
5.0
—
—
x ck
i ck
ns
95 ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle — 2 x T
C
15 — — ns
96 ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK
output
———18.0—ns
97 ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK
output
———18.0—ns
1
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)
2
bl = bit length
wl = word length
wr = word length relative
3
ESAI_TX_CLK(ESAI_TX_CLK pin) = transmit clock
ESAI_RX_CLK(ESAI_RX_CLK pin) = receive clock
ESAI_TX_FS(ESAI_TX_FS pin) = transmit frame sync
ESAI_RX_FS(ESAI_RX_FS pin) = receive frame sync
ESAI_TX_HF_CLK(ESAI_TX_HF_CLK pin) = transmit high frequency clock
ESAI_RX_HF_CLK(ESAI_RX_HF_CLK pin) = receive high frequency clock
4
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
6
Periodically sampled and not 100% tested.
Table 49. Enhanced Serial Audio Interface (ESAI) Timing (continued)
ID Parameter
1,2
Symbol Expression
2
Min Max Condition
3
Unit