Datasheet

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
74 NXP Semiconductors
Electrical Characteristics
4.12.2.1 ECSPI Master Mode Timing
Figure 35 depicts the timing of ECSPI in master mode and Table 47 lists the ECSPI master mode timing
characteristics.
Figure 35. ECSPI Master Mode Timing Diagram
Table 47. ECSPI Master Mode Timing Parameters
ID Parameter Symbol Min Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
• Slow group
1
• Fast group
2
ECSPIx_SCLK Cycle Time–Write
1
ECSPI slow includes:
ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6,
ECSPI2/EIM_OE, ECSPI2/ ECSPI2/CSI0_DAT10, ECSPI3/DISP0_DAT2
2
ECSPI fast includes:
ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0
t
clk
55
40
15
—ns
CS2 ECSPIx_SCLK High or Low Time–Read
• Slow group
1
• Fast group
2
ECSPIx_SCLK High or Low Time–Write
t
SW
26
20
7
—ns
CS3 ECSPIx_SCLK Rise or Fall
3
3
See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”
t
RISE/FALL
——ns
CS4 ECSPIx_SSx pulse width t
CSLH
Half ECSPIx_SCLK period — ns
CS5 ECSPIx_SSx Lead Time (CS setup time) t
SCS
Half ECSPIx_SCLK period - 4 — ns
CS6 ECSPIx_SSx Lag Time (CS hold time) t
HCS
Half ECSPIx_SCLK period - 2 — ns
CS7 ECSPIx_MOSI Propagation Delay (C
LOAD
=20pF) t
PDmosi
-1 1 ns
CS8 ECSPIx_MISO Setup Time
• Slow group
1
• Fast group
2
t
Smiso
21.5
16
—ns
CS9 ECSPIx_MISO Hold Time t
Hmiso
0—ns
CS10 ECSPIx_RDY to ECSPIx_SSx Time
4
4
ECSPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
t
SDRY
5—ns
CS1
CS7
CS2
CS2
CS4
CS6
CS5
CS8
CS9
ECSPIx_SCLK
ECSPIx_SS_B
ECSPIx_MOSI
ECSPIx_MISO
ECSPIx_RDY_B
CS10
CS3
CS3
Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be
connected between a single master and a single slave.