Datasheet

Electrical Characteristics
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018
NXP Semiconductors 73
Figure 32 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For DDR
Toggle mode, the typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI
will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which is
provided by an internal DPLL. The delay value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX
6Dual/6Quad reference manual (IMX6DQRM)). Generally, the typical delay value is equal to 0x7 which
means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot be ignored,
the delay value should be made larger to compensate the board delay.
4.12 External Peripheral Interface Parameters
The following subsections provide information on external peripheral interfaces.
4.12.1 AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.12.2 ECSPI Timing Parameters
This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing
parameters for master and slave modes.
NF28 Data write setup tDS
6
0.25 × tCK - 0.32 — ns
NF29 Data write hold tDH
6
0.25 × tCK - 0.79 — ns
NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ
7
—3.18—
NF31 NAND_DQS/NAND_DQ read hold skew tQHS
7
—3.27—
1
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
AS minimum value can be 0, while DS/DH minimum value is 1.
3
T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
4
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is met automatically by the design. Read/Write operation is
started with enough time of ALE/CLE assertion to low level.
5
PRE_DELAY+1) ≥ (AS+DS).
6
Shown in Figure 30.
7
Shown in Figure 31.
Table 46. Samsung Toggle Mode Timing Parameters
1
(continued)
ID Parameter Symbol
Timing
T = GPMI Clock Cycle
Unit
Min Max